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F2A: V_IN BLOCK DIAGRAM (AJ-YA931G, AJ-YA932G: OPTION)
BLK-3
BUF
LPF
SYNC
SEP
CLAMP
CSYNC
SIGDET
CLP
4
AMP
1st_A/D
KILL_H
AXO
APC_DET
COMP_SYNC
V_DET
SYNC_SEP
PLD_CONF
CMPST_Y
RET_Y
PB_CS/INC/UD
Y_OFS
AMP
2nd_A/D
2nd_A/D
D/A
2nd_A/D
CLAMP
AMP
CLAMP
AMP
CLAMP
PR_CS/INC/UD
LPF
LPF
LPF
Delay ADJ
Delay ADJ
MM
MM
VR3450
SYNC
MM
FF
IC3452<10>
3
1
5
4
MID
W
1
5
7
7
5
PCST
IC3453<10>
IC3400<10>
IC3454<10>
IC3301<7>
IC3301<7>
13
5
7
3
9
IC3454<10>
5
13
4
11
12
9
1
9
1
1
1
IC3456<10>
IC3455<10>
S/H
AMP
TP3450
PLLDC
27M
VCO
VC3450 Q3454
DL3450<10>
131
106
107
108
109
CLK27_ORG
171
177
178
179
36-38
157-162
82,83,
132,133
187-204
M2_L
NENT_L
KILL_H
ADCLK_Y/PB/PR
PB_CS/INC/UD
PR_CS/INC/UD
150
152
147
100-102
97-99
Y_GAIN
PB_GAIN
PR_GAIN
Y_OFS
PB_OFS
PR_OFS
AXO
8
ADCLK_Y
CLAMP
S/H
AMP
4Fsc
VCXO
Y/C SEP.DA
LPF
LPF
AMP
AMP
BPF
C DEM
C DEM
Comparator
LPF
CMPST_Y
CMPST_PB
CMPST_PR
APC_DET
LPF
ADCK
F
rom A
V J
A
CK
F
rom REC PB
F
rom SYSCON
F
rom/T
o SYSCON
F
rom/T
o PLD
Wr
iter
Via.
REAR J
A
CK
F
rom A
V J
A
CK
6A
6B
6C
7A
7C
27B
27C
26A
27A
7C
7B
9B
Q3500<11>
Q3501<11>
Q3502<11>
10B
11B
BUF
BUF
BUF
M2_L
NENT_L
P3001
P100
P3001
P3001
P3001
P1
P3001
P3001
P3001
P3001
P1
P100
P1
8B
24B
P100
P100
P100
27D
23B
23C
23D
17C 12A
26C 26C
27A 27A
26B 26B
22A 22B
Q3100<3>
Q3150-3154<4>
IC3152<4>
IC3201<5>
Q3250,L3253
C3256<6>
Q3252,Q3255
Q3257<6>
Q3253,Q3254
Q3255<6>
Q3352,L3354
C3371<8>
Q3353,L3355
C3372<8>
Q3260
Q3261<6>
AXSU
AXSU
8
1
12
12
1
IC3351<8>
P3001
P3001
P3001
P3001
P3002
P3001
IC3871<17>
IC3822<16>
IC3870<17>
IC3352<8>
IC3350<8>
IC3820<16>
DEC_CTL FPGA (PLD)
7
144
2
3-18
1,19
11
15
17
13
8
2-17
19
9
12
5
3
7
44-51
20
21
22
145
134
9
Income Burst Flag
4fsc PLL
Q3251,L3254
C3258<6>
Q3300<7>
IC3457<10>
13
17
LINE
COMP_SYNC3
CCLP
110
146
11
9
4
111
113
3
3
4
10
5
6
5
14
1
IC3304<7>
IC3302<7>
X3300
<7>
FL3100<3>
IC3100<3>
IC3101<3>
IC3150<4>
Q3156
18
24
78
39
31
13
14-16
71 11
13
2
2
7
8
15
5
16
AIN_L
IN_BUFF
IN_BUFF
BUFF
ROM
for FPGA
AV_BUS
2-9
2-9
4
6
8
18
13
25
32
28
2,7,
10,31
IC3530<12>
FL3530<12>
FL3600<13>
FL3700<14>
IC3601<13>
IC3534<12>
IC3532<12>
IC3604<13>
1-3
IC3800<15>
EVR_D
A
T
A/CLK/LD
38,39
41,42
44,45
40
43
46
47
IC3704<14>
Q3602-9<13>
Q3702-9<14>
IC3531,
Q3539<12>
IC3701<14>
14
9
9-11
1
5
18
14
9-11
1
5
14
9-11
1
5
9
1
16
14
12
2
4
7-9
3
5
2
16
11-13
17
15
18
1
DIR
19
11-18
OE
IC3900<18>
IC3902<18>
IC3950<19>
IP3950<19>
IC3901<18>
NENT_L
RET_Y
VIDEO_IN
ISP_TDI
ISP_TMS
ISP_TCK
ISP_TDO
CONF_INFO
ISP_SEL1
Y_IN
PB_IN
PR_IN
AIN_L
AV_ADRS[0-10]
AV_IOWR_L
AV_RST_L
AV_IORD_L
AV_CS_VIN_L
AV_DATA[0-7]
TBC_WH
TBC_WH
REC_YC(7..0)
T
o REC_PB
OUT_BUFF
OUT_BUFF
EEPROM
SYNC_HD
TBC_WH
AIN_L
CF
FRM
MD
COMP
SYNC
CLK27
ORG
AV_BUS
PLD_CONF
INCOM_CLK27
VBLK_CSYNC
INCOM_CF
INCOM_FRM
INCOM_HD
21C
14C
16A
24B
24C
19A
21A
19B
21B
19C
20C
18A
18B
18C
22A
18A
18B
18C
TBC_WV
RSTH SITE
5
SCH SITE
CLAMP_Y
CLAMP_C
14
11
11
3
1
3
7,8
7,8
1
5
3
24
24
24
IC3602,
Q3608<13>
<14>
3
2
6
10
13
13
12
12
3
3
5
8
TP3301
BGP
TP3300
APC
TP3821
CF1
TP3870
INCF
TP3871
INFRM
TP3822
CF2
TP3823
TP3824
SC HP
CMPST_PB
CMPST_PR
Y_GAIN
18,22
13
18,22
18,22
PB_GAIN
ADCLK_PR
ADCLK_PB
PR_GAIN
PB_OFS
PR_OFS
MM
VR3301
SCH
MM
VR3300
RSTH
IC3600<13>
IC3700<14>
1
1
8
8
8
T
o SYSCON
19A
21A
19B
21B
19C
20C
23A
26A
23B
25B
22C
25C
23A
26A
23B
25B
22C
25C
28A
29A
27B
29B
27C
29C
28A
29A
27B
29B
27C
29C
NTSC only
Summary of Contents for AJSD955B - DVCPRO50 STUDIO DECK
Page 3: ...3...
Page 4: ...4 AJ YA931G AJ YA932G AJ YAC930G...
Page 6: ...6 AJ SD930P AJ SD955AP...
Page 7: ...7 AJ YA931G AJ YA932G AJ YAC930G...
Page 8: ...FCD0211NTIK83K84...
Page 65: ...INF 56 14 ERROR MESSAGES...
Page 66: ...INF 57...
Page 67: ...INF 58...
Page 72: ...INF 63 16 CIRCUIT BOARD LAYOUT DRAWING...
Page 105: ...MECH 26 Figure 3 32 3 Figure 3 32 4 Adjust within specification Confirm this value...
Page 109: ...MECH 30 Figure 3 34 3 Figure 3 34 4 Adjust within specification Confirm this value...
Page 111: ...MECH 32 Figure 3 35 2 Confirm this value...