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F1: AUDIO BLOCK DIAGRAM
BLK-2
SW4100<2>
P4001
P100
8C
8D
8B
8C
7D
7B
7C
6D
6B
6C
5D
5B
5C
CH1 IN H
8B
CH1 IN G
8A
CH1 IN C
P4001
P100
P4001
P100
P4001
P100
9C
CH2 IN H
9B
CH2 IN G
9A
CH2 IN C
10C
CH3 IN H
10B
CH3 IN G
10A
CH3 IN C
11C
CH4 IN H
11B
CH4 IN G
11A
CH4 IN C
P4001
P4001
26A
AV ADRS0
23B
AV ADRS8
23A
AV ADRS9
22C
AV ADRS10
P4001
13C
CH1 OUT H
13B
CH1 OUT G
13A
CH1 OUT C
P4001
P4001
P4001
14C
CH2 OUT H
14B
CH2 OUT G
14A
CH2 OUT C
15C
CH3 OUT H
15B
CH3 OUT G
15A
CH3 OUT C
16C
CH4 OUT H
16B
CH4 OUT G
16A
14D
14B
14C
13D
13B
13C
12D
12B
12C
11D
11B
11C
CH4 OUT C
P4001
P100
P4001
P100
P100
P100
P100
P100
17C L MONI OUT H
17B L MONI OUT G
17A L MONI OUT C
18C R MONI OUT H
18B R MONI OUT G
18A
10D
9D
10C
10B
9B
10A
R MONI OUT C
P100
P5901
P5901
P4002
P4002
P4002
MONI_L
P100 P4002
MONI_R
29B
HPR
29A
1
3
HPL
19A CUE REC OUT
19C
9B
CUE PB IN
7B
27A
AV RST L
26B
AV IORD L
26C
AV IOWR L
27B
AV DATA(7)
27C
AV DATA(6)
28A
AV DATA(5)
28B
AV DATA(4)
28C
AV DATA(3)
29A
AV DATA(2)
29B
AV DATA(1)
29C
AV DATA(0)
MUT
Q500
H.P
OUT R
H.P
OUT L
CUE R/P
HEAD
CTL
ERASE
HEAD
CUE
ERASE
HEAD
Q501
MUT
Q4828
Q4829
MUT
AMP
IC507<5>
VR505
Q4006,7,8,9<6>
TP4006
VR4001
TP4005
IC4002<6>
IC4001<6>
3
5
1
6
5
7
1
5
IC507<5>
MUT
R/P
HSW
CUE BIAS
OSC
BIAS CURR
DUMM
CUE/CTL
ERASE OSC
PB EQ
AMP
REC EQ
AMP
AMP
VR
H.P(FRONT)
RF/CUE(1/2)
CUE_INS_H
TP4001
T4003
T4001
RY4001
L4004
7
1
2
6
AMP
IC4832<8>
IC4832<8>
AMP
CYL.N
CANCEL
ATT
PB
EE
IC5001<10>
VR5006
REC CURR
VR5001
CYL FG
IC4813,4814<10>
PB LEVEL
CUE PB
AMP
INPUT IMPEDANCE
SEL SW
HIGH/600
A/D
BUFF
BCK
LRCK
MCK
BUFF
A/D
IC4306<4>
IC4300<4>
ADSD12
IC4307<4>
ROM
for FPGA
AVCNT-FPGA (PLD)
BUFF
IP5400<13>
IC5401
IC4300<4>
D/A
IC4450<5>
DASDLR
DASD34
DASD12
BCK1
WCK1
MCK1
CH1 IN LEVEL
2
3
9,10
9,10
1
(FS:48KHz)
FS64
ADSD34
(FS256)
7
18
16
2
13
3
4
12
17
8
13
11
12
11
10
13
12
SW4101<2>
INPUT IMPEDANCE
SEL SW
HIGH/600
2
1
SW4200<3>
INPUT IMPEDANCE
SEL SW
HIGH/600
2
3
3
3
2
1
SW4201<3>
IC5404<13>
INPUT IMPEDANCE
SEL SW
HIGH/600
IC4100,4102<2>
INPUT LEVEL SEL
(-60)/-20/0/+4
IC4101,4103<2>
INPUT LEVEL SEL
(-60)/-20/0/+4
IC4200.4202<3>
INPUT LEVEL SEL
(-60)/-20/0/+4
IC4201,4203<3>
INPUT LEVEL SEL
(-60)/-20/0/+4
IC4106<2>
BAL.AMP
IC4107<2>
BAL.AMP
IC4206<3>
BAL.AMP
IC4207<3>
IC4952<9> (1/2)
BAL.AMP
IC4110,4112<2>
REF.LEVEL SEL
FS-20/-18/-12
IC4111,4113<2>
REF.LEVEL SEL
FS-20/-18/-12
IC4210,4212<3>
REF.LEVEL SEL
FS-20/-18/-12
IC4211,4213<3>
REF.LEVEL SEL
FS-20/-18/-12
BUFFER
IC5402<13>
BUFFER
P.ON
MUTE
MUTE
DRIVE
Q4566,4568<6>
Q4450,4451
QR4450,4451
+12V
IC4564,4566<6>
MUT
OUTPUT
BAL AMP
IC4560,4562<6>
OUTPUT LEVEL
SEL.
-20/0/+4
CH1 IN SEL(1.0)
REF SEL(1,0)
CH2 IN SEL(1.0)
CH3 IN SEL(1.0)
CH4 IN SEL(1.0)
CH1 OUT SEL(1.0)
MUTE H(F
or HP
. MONIT
OR)
P MUTE H(F
or LINE)
L OUT SEL(1,10)
R OUT SEL(1,10)
CH2 OUT SEL(1.0)
CH3 OUT SEL(1.0)
CH4 OUT SEL(1.0)
2
1
25C
MCK1
P4002
24C
P4002
P4001
25B
WCK1
25A
24B
25C
P4001
24B
P4001
24C
25B
25A
BCK1
ADSD34
ADSD12
26A 26A
CUE MET DATA
26B 26B
CUE MIX DATA
2
TDO
P5400
P4002
3
TDI
6
TMS
8
TCK
TP4560
Q4567,4569<6>
IC4565,4567<6>
MUT
OUTPUT
BAL AMP
IC4561,4563<6>
OUTPUT LEVEL
SEL.
-20/0/+4
TP4561
Q4696,4698<7>
IC4694,4696<7>
MUT
OUTPUT
BAL AMP
IC4690,4692<7>
OUTPUT LEVEL
SEL.
-20/0/+4
TP4690
Q4697,4699<7>
IC4695,4697<7>
MUT
OUTPUT
BAL AMP
IC4691,4693<7>
OUTPUT LEVEL
SEL.
-20/0/+4
IC4822,4826<8>
OUTPUT LEVEL
SEL.
-20/0/+4
IC4823,4828<8>
OUTPUT LEVEL
SEL.
-20/0/+4
TP4691
Q4824,4826<8>
IC4827,4830<8>
MUT
OUTPUT
BAL AMP
TP4820
Q4825,4827<8>
IC4829,4831<8>
MUT
OUTPUT
BAL AMP
IC4453,4457<5>
REF. LEVEL SEL
FS-20/-18/-12
IC4309,4313<4>
REF. LEVEL SEL
FS-20/-18/-12
IC4310,4314<4>
REF. LEVEL SEL
FS-20/-18/-12
IC4311,4315<4>
REF. LEVEL SEL
FS-20/-18/-12
IC4312,4316<6>
REF. LEVEL SEL
FS-20/-18/-12
REF. LEVEL SEL
FS-20/-18/-12
IC4454,4458<5>
TP4821
TP5200
TP5200
9,10
163 162
9,10
9,10
9,10
9,10
9,10
AV_DATA
2
2
IC5002,5003<10>
IC5011<10>
LIM
AMP
IC5203<11>
NR
CODEC
(A/D)
(D/A)
IC5009<10>
IC5202<11>
IC4952<9> (2/2)
REC OUT
AINR
AINL
AOUTL
AOUTR
IC5004<10>
AMP
12
13
1
3
2
14
6
8
11
10
12
11
3
2
3
4
18
17
16
9
9
7
5
8
12
13
CUE_ADSD
CUE_DASD
CUE-EE :
EE
204
205
PB
R
L
EE/PB
REC
DELAY
PB
DELAY
FS-20/-18/-12
FS-20/-18/-12
FS
206
192
193
203
P4002
P4001
P4002
24A 24A
DASD LR
P4002
23B 23B
DASD 12
P4002
23C 23C
DASD 34
P4002
P4001
P4001
P4001
P4001
T
o/F
rom A_PR
OC
F
rom A_PR
OC
IC4463<5>
VR4450
L OUT LEVEL
R OUT LEVEL
AMP
D/A
IC4307<4>
26
14
28
D/A
IC4306<4>
26
15
14
14
28
6
5
VR4451
IC4560<6>
VR4560
CH1 OUT LEVEL
AMP
IC4561<6>
VR4561
CH2 OUT LEVEL
AMP
IC4690<7>
VR4690
CH3 OUT LEVEL
AMP
IC4691<7>
VR4691
CH4 OUT LEVEL
AMP
IC4464<5>
AMP
BCK1
WCK1
MCK1
7A
ISP TDO
P4001
6A
ISP TDI
6B
ISP TMS
6C
ISP TCK
VR4300
4
IC4301<4>
AMP
CH2 IN LEVEL
VR4301
CH3 IN LEVEL
VR4302
CH4 IN LEVEL
VR4303
2
3
IC4302<4>
AMP
4
5
IC4303<4>
AMP
2
3
IC4304<4>
AMP
2
F
rom
V_IN,A_PR
OC
,SDI,SYSCON,SDTI,REC_PB
T
o A
V J
A
CK
F
rom A
V J
A
CK
T
o PLD
WRITER
VIA REAR J
A
CK
F
rom A_PR
OC
T
o A_PR
OC
T
o A_PR
OC
22B
22B
P1
AV CS AUDIO L
P4001
F
rom
SYSCON
BUFF
IC5200<11>
1
2
3
4
1
2
3
4
5
5
Summary of Contents for AJSD955B - DVCPRO50 STUDIO DECK
Page 3: ...3...
Page 4: ...4 AJ YA931G AJ YA932G AJ YAC930G...
Page 6: ...6 AJ SD930P AJ SD955AP...
Page 7: ...7 AJ YA931G AJ YA932G AJ YAC930G...
Page 8: ...FCD0211NTIK83K84...
Page 65: ...INF 56 14 ERROR MESSAGES...
Page 66: ...INF 57...
Page 67: ...INF 58...
Page 72: ...INF 63 16 CIRCUIT BOARD LAYOUT DRAWING...
Page 105: ...MECH 26 Figure 3 32 3 Figure 3 32 4 Adjust within specification Confirm this value...
Page 109: ...MECH 30 Figure 3 34 3 Figure 3 34 4 Adjust within specification Confirm this value...
Page 111: ...MECH 32 Figure 3 35 2 Confirm this value...