OPTO 22 PCI-AC48, User Manual

Page: 26 / 28

REGISTER TABLE
PCI-AC48 User’s Guide
22
Register Table
Address
1
Register Read/
write
2
Bits
7 6 5 4 3 2 1 0
0
RHR receive
holding register
R X
3
X X X X X X X
THR transmit
holding register
W X X X X X X X X
LSB of divisor
latch when
DLE=1
W X X X X X X X X
1
IER interrupt
enable register
W 0
4
0 0 0
modem
status
interrupt
5
receive
line sta-
tus inter-
rupt
transmit
holding
register
interrupt
receive
holding
register
interrupt
MSB of divisor
latch where
DLE=1
W X X X X X X X X
2
FCR, FIFO
control register
W
RCVR
trigger
MSB
RCVR
trigger
LSB
0 0
DMA
mode
select
transmit
TITO
reset
receiver
FIFO
reset
FIFO
enable
ISR interrupt
status register
R
0/FIFO
enabled
0/FIFO
enabled
0 0
interrupt
prior. bit
2
interrupt
prior. bit
1
inter-
rupt
prior. bit
0
inter-
rupt sta-
tus
3
LCR line con-
trol register
W
DLE
divisor
latch
enable
6
set
break
set par-
ity
even
parity
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
4
MCR modem
control register
W 0 0 0
loop
back
OP2 OP1 RTS DTR
5
LSR line status
register
R
0/FIFO
error
trans-
mit
empty
trans-
mit
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
6
MSR modem
status register
R CD RI DSR CTS delta-CD delta-RI
delta-
DSR
delta-
CTS
7
SPR scratch
pad register
R/W X X X X X X X X
1
Address of register (0–7)
2
Some registers are read/write, some are write-only, some are read-only, and some have different purposes when reading or writing.
3
X = a data bit, either 1 or 0.
4
0 = must be zero when writing
5
The delta-CTS bit indicates if the CTS bit has changed, and this interrupt can be enabled by setting the modem status interrupt of the
IER.
6
The divisor latch enable bit or the LCR determines the mode of the registers at offset 0 and 1.