912-3000-042
Revision: 1.0
July 15, 1997
OPTi
®
MachOne™
82C935
Integrated PCI Audio Processor
Data Book
Page 1: ...912 3000 042 Revision 1 0 July 15 1997 OPTi MachOne 82C935 Integrated PCI Audio Processor Data Book...
Page 2: ...porated 888 Tasman Drive Milpitas CA 95035 Disclaimer OPTi Inc makes no representations or warranties with respect to the design and documentation herein described and especially disclaims any implied...
Page 3: ...8 1 I2S justified format and its variations 12 4 8 2 Sony format 12 4 8 3 AT T PCM codec T7525 compatible 16 bit mono format 12 4 8 4 Testing I2S format ZV port with Audio Precision machine 13 4 8 5 R...
Page 4: ...pecifications 5 0 Volt VCC 5 0V 5 TA 0 C to 70 C 45 6 4 Pin Specifications Analog VCC 5 0V 25 C 46 6 5 Volume Setting 46 6 6 Analog Characteristics 46 6 6 1 Analog Inputs 47 6 6 2 Analog Outputs 10kW...
Page 5: ...mplified Functional Block Diagram 3 Figure 3 1 128 Pin PQFP LQFP Pin Diagram 4 Figure 4 1 Functional Block Diagram 10 Figure 4 2 Mixer Block Diagram 11 Figure 4 3 I2S Format 14 Figure 4 4 General Purp...
Page 6: ...G 40h FFh 23 Table 5 4 MCIdx and MCData Registers 29 Table 5 5 MC Indirect Registers 29 Table 5 6 Extended MC Register Group MCIdx 20h 2Fh 34 Table 5 7 SBBase Registers for FM and DAP Applications 36...
Page 7: ...dio software enhancements including wavetable and 3D positioning acceleration mak ing the MachOne an ideal gaming platform The Digital Game Port Timer improves overall system performance by offload in...
Page 8: ...our programmable I O pins 5V voltage supply Support ACPI power down mode Digital PC Speaker support 20 bit 1 s resolution DirectX timer 128 pin LQFP package or 128 pin PQFP package Figure 2 1 System B...
Page 9: ...l Audio Interface PCI Interface Distributed Virtual DMA Logic Interrupt Game Port Timer MUX CODEC MIXER Volume Control UART CLK GEN CONF REGS Interface 33MHz EEPROM SIN GD 7 0 AUXL R MIXOUTL R MICL R...
Page 10: ...3 112 111 110 109 108 107 106 105 104 103 AUXR VREF1 AVDD AVSS AVSS AVDD OSCI OSCO RXD TXD GPIO0 GPIO1 SCLK1 SDI1 SDO1 SLR1 GND GD0 GD1 GD2 GD3 GD4 GD5 GD6 GD7 VOLUP VOLDWN VCC INTB INTC 45 46 47 48 4...
Page 11: ...E1 67 CBE2 59 CBE3 48 CDL 123 CDR 128 CINL 118 CINR 116 CLK 35 DEVSEL 63 FRAME 60 GD0 18 GD1 19 GD2 20 GD3 21 GD4 22 GD5 23 GD6 24 GD7 25 GND 17 GND 34 GND 49 Signal Name Pin GND 65 GND 76 GND 86 GND...
Page 12: ...arget Ready PCI Bus DEVSEL 63 I O TTL SMT pull up Device Select PCI Bus STOP 64 I O TTL SMT pull up Stop cycle PCI Bus IDSEL 47 I TTL SMT Initialization Device Select PCI Bus RST 33 I TTL SMT Reset PC...
Page 13: ...AC97 SYN 93 O TTL AC97 SYN AC97 SDO 94 O TTL AC97 Serial Data Out AC97 SDI 101 I TTL AC97 Serial Data In General Purpose Bit I O GPIO 3 0 103 102 12 11 I O TTL General Purpose Bit I O Volume Control...
Page 14: ...I Analog Analog Digital Convertor Filter Left Right ANALOG VREFI 2 O Analog Analog Reference ANALOG VREF 112 O Analog Voltage Reference ANALOG OSCI 7 I Analog Oscillator Input OSCO 8 O Analog Oscilla...
Page 15: ...speakers The following block diagram shows the functional element of the 3D sound enhance processor in the 82C935 4 4 16 Bit Type F DMA Playback The 82C935 supports the Type F DMA playback 4 5 Push B...
Page 16: ...he frequency of MCLK is 256 times the sampling frequency The DAC left right 16 bit input data are multiplexed onto DAC 15 0 and fed into the codec The L R signal qualifies the data The period of L R i...
Page 17: ...UTL mixer record output left must be connected to CINL codec analog input left with a ceramic capacitor MIX OUTR mixer record output right must be connected to CINR codec analog input right with a cer...
Page 18: ...mes LRCLK period is greater than 32 SCLKs Please note that in ZV port there is one more signal MCLK defined but this is not needed for the 935 To program the 935 in the I2 S justified mode the MC22 an...
Page 19: ...LK32 Specifies the number of SCLKs per LRCLK period used only in delay mode or pulse mode ASIO 0 32 SCLK per LRCLK period 1 more than 32 SCLK per LRCLK period Bit 3 SCLK polarity 0 SDATA and LRCLK cha...
Page 20: ...he required MCLK and LRCLK fre quencies Typically most devices operate with 384fx master clock The ZV Port audio DAC should support an MCLK frequency of 384fs This results in the frequencies shown bel...
Page 21: ...DATA INPUT SETUP TIME to bit clock falling edge 30nS minimum 4 DATA INPUT HOLD TIME from bit clock falling edge 45nS minimum 4 8 8 TDA1311 Stereo Continuous Calibration Figure 4 5 Format of Input Sign...
Page 22: ...served Cap_Ptr 34h Reserved 38h Max_lat Min_Gnt Interrupt Pin Interrupt Line 3Ch PCI Extended Mode Register Group PCICFG 40h FFh Power Control Latch Registers 1 4 40h DMA Channel Selector Registers 1...
Page 23: ...ter Values MCIR25 FDAC Data Control MCIR26 Reserved MCIR27 31 Extended MC Register Group AC LINK Index MCRI32 AC LINK Data MCIR33 AC LINK Control MCIR34 Extended Digital Power Management MCIR35 Extend...
Page 24: ...c only WSBase 05h Codec Status R W exists in Codec only WSBase 06h Codec Direct Data R W exists in Codec only WSBase 07h Codec Indirect Registers MIXOUTL Output Control CIR0 MIXOUTR Output Control CIR...
Page 25: ...e Reserved IO Enable Response to IO PCICFG 05h PCI Command Register Byte 1 Bits 15 8 Default 00h Reserved Write bits as read PCICFG 06h PCI Status Register Byte 0 Bits 7 0 Default 00h Reserved UDF Use...
Page 26: ...Default 00h SBA SB Compatible Base Address RO SBA SB Compatible Base Address RW PCICFG 12h SB Compatible Base Address Byte 2 Bits 23 16 Default 00h SBA SB Compatible Base Address RO PCICFG 13h SB Comp...
Page 27: ...IDI Base Address Byte 3 Bits 31 24 Default 00h MIDIA MIDI Base Address RO PCICFG 20h Game Port Compatible Base Address Byte 0 Bits 7 0 Default 01h GPA Game Port Compatible Base Address RW Indicates th...
Page 28: ...CFG 2Fh Subsystem ID Register RO Byte 1 Bits 15 8 Default 00h PCICFG 30h 33h Reserved Default 00h PCICFG 34h Capability Pointer RO Default DCh Pointer to a linked list of additional Capabilities List...
Page 29: ...lt 101 Channel 5 010 Channel 2 110 Channel 6 011 Channel 3 111 Channel 7 Channel 0 0 Not claimed 1 On docking ISA DRQ0 DACK0 pin 000 Channel 0 Default 100 Reserved 001 Channel 1 101 Channel 5 010 Chan...
Page 30: ...10 IRQ10 1110 IRQ14 0011 IRQ3 0111 IRQ7 1011 IRQ11 1111 IRQ15 PCICFG 4Bh IRQ Channel Selector Register 4 Default BAh IRQ11 pin Default IRQ11 0000 IRQ0 0100 IRQ4 1000 IRQ8 1100 IRQ12 0001 IRQ1 0101 IRQ...
Page 31: ...nction select 0 DRD DWR 1 DBE0 DBE1 CHCK pin active halts ISA bus 0 No normal CHCK 1 Yes HDI function Flash EEPROM writes 0 Disable SMWR is blocked also 1 Enable IRQ8 active level 0 Low 1 High DMA reg...
Page 32: ...0 5FFFh 110 6000 6FFFh 111 7000 7FFFh AEN1 high for x000 x3F8h 0 No 1 Yes AEN1 enabled low for I O range 000 0000 FFFFh normal AEN 001 1000 1FFFh 010 2000 2FFFh 011 3000 3FFFh 100 4000 4FFFh 101 5000...
Page 33: ...G 63h Reserved Default 00h PCICFG 64h DDh Reserved Default 00h PCICFG DEh Power Management Capabilities Byte 0 Bits 7 0 RO Default 00h Reserved DynClk This field is used by a bridge to inform the syst...
Page 34: ...gement Control Status Byte 1 Bits 15 8 Default 00h Reserved Func_Int Indicates the cur rent state of the function s stan dard interrupt RO StatChg_Int Indicate a status change interrupt Independent of...
Page 35: ...0 GPIO Control 01000 MCIR8 Reserved 10101 MCIR21 Serial Audio Control 01001 MCIR9 Test Control 10110 MCIR22 Serial Audio Control 01010 MCIR10 Test Control 10111 MCIR23 Reserved 01011 MCIR11 Status Rem...
Page 36: ...rved Codec Expanded Mode 1 0 Disable 1 Enable Sound Blaster ADPCM 0 Disable 1 Enable CommandFIFO in Sound Blaster mode 0 Disable 1 Enable Volume effect for Sound Blaster Pro mixer voice vol ume emulat...
Page 37: ...ce 0 Disable 1 Enable CONFIG mode 1 82C935 s PNP logic is in the CONFIG mode ISOLATE mode 1 82C935 s PNP logic is in the ISOLATE mode SLEEP mode 1 82C935 s PNP logic is in the SLEEP mode WAIT4KEY mode...
Page 38: ...nhanced FM features 0 Disable 1 Enable External FM select 0 Disable 1 Enable MCIR20 GPIO Control Register 0 Default 00h GPIO3 Output Values at Pin 103 GPIO3 pin type 0 Input 1 Output GPIO2 Output Valu...
Page 39: ...ial audio data output sclk_out 00 mclk 8 01 mclk 4 10 mclk 2 11 mclk 1 MCIR24 Game Port Counter Setup and Status Register Default 00h JRDY Game Port IRQ Readback of 1 indicates the game port counters...
Page 40: ...ct Registers cont 7 6 5 4 3 2 1 0 Table 5 6 Extended MC Register Group MCIdx 20h 2Fh 7 6 5 4 3 2 1 0 MCIR32 AC LINK Index Register R W Default 00h Always 0 AC97 Mixer Index Register MCIR33 AC LINK Dat...
Page 41: ...e SLR2 Output Enable ASIO2Select 1 Select 2nd ASIO output 3D Space Control 00 Bypass 01 QX1 MIN 10 QX2 11 QX3 MAX MCIR38 Functional Interrupt Status Register RO Default 00h Reserved GPI Game Port Inte...
Page 42: ...P software reset at end of the I O write command 0 Disable 1 Enable 1 1 When bit 0 is enabled it sets a software reset flag This software reset is terminated by performing another write at this locati...
Page 43: ...Indirect SBBase 0Eh DAP Output Buffer Status Register RO DAP output buffer is full 1 0 Empty 1 Full Output Buffer 1 This flag is set in the DAP when data is written in the output data bus buffer and...
Page 44: ...itial value of this register will be 0100 0000 40h During codec initialization the Codec Index Register cannot be written and is always read 1000 0000 80h 2 When bit 5 is set DMA transfers cease when...
Page 45: ...er PD7 0 Reads will receive data from the PIO Capture Data Register CD7 0 During initialization the PIO Playback Data Register cannot be written and the Capture Data Register is always read 1000 0000...
Page 46: ...r Default 00h Audio data format linear PCM or companded for all input and output data used in conjunction with bit 5 1 000 Linear 8 bit unsigned 001 law 8 bit companded 010 Linear 16 bit two s complem...
Page 47: ...t when capture data has not been read by the host before the next sam ple arrives The sample being read will not be overwritten by the new sam ple The new sample is ignored Playback underrun 1 This bi...
Page 48: ...ack and Capture Base Registers Table 5 11 Expanded Mode CIR 7 6 5 4 3 2 1 0 CIR16 AUXL Input Control Register Default 88h Mute 0 Disable 1 Enable Reserved Gain select for AUXL dB Refer to CIR2 4 1 for...
Page 49: ...ved Note Bit 7 is not available in Mode 1 forced to 0 Stereo mono 2 0 Mono 1 Stereo Reserved 1 SB WSS mode switch In Sound Blaster mode the software driver should set CDF to 8 bit PCM mode R8 FM1 FM C...
Page 50: ...tions are recommended to avoid performance degradation or loss of functionality Symbol Parameter Min Max Unit VCC Supply Voltage 4 5 5 5 V AVCC Analog Supply Voltage 4 75 5 25 V VIN Input Voltage 0 5...
Page 51: ...CMOS STATIC VH Schmitt Hysteresis 0 6 1 0 V TTL STATIC CMOS STATIC VIL low Level Input Voltage 0 8 V TTL STATIC VIH High Level Input Voltage 2 0 V TTL STATIC VOL Low Level Output Voltage 0 4 V TTL ST...
Page 52: ...20K 3 0 Hz V Sine Wave Load 10K 25pF MIXOUTR MIXOUTL Signal Bandwidth Output Range 10 20K Hz Sine Wave VREF1 VREF2 1 75 1 85 V DC DC Parameter Min Typ Max Unit Test Conditions Input Gain Atten Range...
Page 53: ...Parameters Min Typ Max Units Input voltage LINE CD AUX CIN 2 6 2 8 3 1 Vp p MIC with 0dB gain 2 6 2 8 3 1 Vp p MIC with 20dB gain 0 26 0 28 0 31 Vp p Input impedance 10 20 k Input capacitance 15 pF Pa...
Page 54: ...ts Resolution 16 bits Total dynamic range 75 85 dB THD 025 Interchannel isolation Line to Line CD Aux Mic 80 dB Interchannel gain mismatch 0 5 0 5 dB Gain drift 100 ppm C Parameters Min Typ Max Units...
Page 55: ...MachOne OPTi 912 3000 042 Page 49 Revision 1 0 7 0 Mechanical Package Outlines Figure 7 1 128 Pin PQFP LQFP Refer to Table 4 1 for PQFP Variable Dimensions and Table 4 2 for LQFP Variable Dimensions...
Page 56: ...cannot be located on the lower radius or the lead foot Symbol Millimeter Inch Min Nom Max Min Nom Max A 3 40 0 134 A1 0 25 0 010 A2 2 50 2 72 2 90 0 098 0 107 0 114 b 0 170 0 200 0 270 0 007 0 008 0...
Page 57: ...the lead foot Minimum space between protrusion and an adjacent lead is 0 07mm for 0 4mm and 0 5mm pitch packages Symbol Millimeter Inch Min Nom Max Min Nom Max A 1 60 0 063 A1 0 05 0 15 0 002 0 006 A...
Page 58: ...MachOne OPTi Page 52 912 3000 042 Revision 1 0...
