NCP1201
http://onsemi.com
15
As shown below, the fault logic is armed once
V
CC
crosses
10 V after startup phase. When powering the device from an
auxiliary winding, meeting this condition can sometimes be
problematic since upon startup,
V
CC
naturally goes up and
not down as with a DSS. As a result,
V
CC
never crosses 10 V
and the fault logic is not activated. If a short−circuit takes
place, the fault circuitry activates as soon as
V
CC
collapses
below 10 V (because of the coupling between
V
aux
and
V
out
), but in presence of a broken optocoupler, i.e. feedback
is open,
V
CC
increases and the fault will never triggered! To
avoid this problem, the application note “Tips and Tricks
with NCP1200, AN8069/D” offers some possible solutions
where the DSS is kept for protection logic operation only but
all the driving power is derived from the auxiliary winding.
Some solutions even offer the ability to disable the DSS in
standby and benefit to low standby power.
Figure 34. Fault Protection Timing Diagram
Regulation
occurs here
Overload is
not activated
Overload is
activated
Driver
Pulses
Latched−off
Fault occurs here
Regulation
Open−loop
FB level
V
CC
12 V
10 V
No synchronization
between DSS and
fault event
Time
Time
Time
Drv
FB
Calculating the V
CC
Capacitor
As the above section describes, the fall down sequence
depends upon the
V
CC
level, i.e. how long does it take for the
V
CC
line to decrease from 12.5 V to 10.5 V. The required
time depends on the powerup sequence of your system, i.e.
when you first apply the power to the device. The
corresponding transient fault duration due to the output
capacitor charging must be less than the time needed to
discharge from 12.5 V to 10.5 V, otherwise the supply will
not properly startup. The test consists in either simulating or
measuring in the laboratory to determine time required for
the system to reach the regulation at full load. Let’s assume
that this time corresponds to 6.0 ms. Therefore a
V
CC
fall
time of 10 ms could be well appropriated in order to not
trigger the overload detection circuitry. If the corresponding
IC consumption, including the MOSFET drive, establishes
at 1.8 mA for instance, we can calculate the required
capacitor using the following formula:
D
t
+
D
V
C
i
, with
D
V = 2.0 V. Then for a wanted
D
t of 10 ms, C equals 9.0
m
F
or 10
m
F for a standard value. When an overload condition
occurs, the IC blocks its internal circuitry and its
consumption drops to 575
m
A typical. This explains the
V
CC
falling slope changes after latchoff in Figure 34.
