ON Semiconductor NCN49597, Manual, Page: 19 / 28

NCN49597
http://onsemi.com
19
6 bit @ 300 baud
t
10 ms
V
MAINS
ZeroCross
t
ZCD
VIR
ZC _IN
CHIP _CLK
PC 20090 619 .3
PLL in lock
Start of Physical PreFrame (*)
*The start of the Physical Subframe is shifted back with R_ZC_ADJUST[7:0] x 26 m S = t
ZCD
to compensate for the zero cross delay.
Figure 12. Zero Cross Adjustment to Compensate for Zero Cross Delay (example for 50 Hz)
The phase difference between the zero cross of the mains
and CHIP_CLK can be tuned. This opens the possibility to
compensate for external delay t
ZCD
(e.g. opto coupler) and
for the 1.9 V positive threshold VIR
ZC_IN
of the zero cross
detector. This is done by pre − loading the PLL counter with
a number value stored in register R_ZC_ADJUST[7:0]. The
adjustment period or granularity is 26
m
s. The maximum
adjustment is 255 x 26 m s = 6.6 ms which corresponds with
1/3rd of the 50 Hz mains sine period.
Table 19. ZERO CROSS DELAY COMPENSATION
R_ZC_ADJUST[7:0] Compensation
0000 0000 0 m s
0000 0001 26 m s
0000 0010 52 m s
0000 0011 78 m s
… …
1111 1101 6589 m s
1111 1110 6615 m s
1111 1111 6641 m s
Oscillator
The oscillator works with a standard parallel resonance
crystal of 48 MHz. XIN is the input to the oscillator inverter
gain stage and XOUT is the output.