ON Semiconductor NCN49597, Manual, Page: 15 / 28

NCN49597
http://onsemi.com
15
Functional Description
The block diagram below represents the main functional units of the NCN49597:
Communication Controller
ARM
Risc
Core
Serial
Comm.
Interface
Local Port
Test
Control
POR
Watchdog
Timer 1 & 2
SPI
Interrupt
Control
Data
RAM Program
ROM
AAF AGC A/D
REF
S − FSK
Demodulator
Receiver (S − FSK Demodulator)
Clock and Control
Zero
crossing
PLL OSC
Clock Generator
& Timer
Transmit Data
& Sine Synthesizer
D/A
LP
Filter
Transmitter (S − FSK Modulator)
RX_DATA
RESB
JTAG I /F
TEST
TX_ENB
TX_OUT
ALC_IN
RX_OUT
RX_IN
REF_OUT
M50Hz_IN
XIN XOUT VDDA VSSA VDDD VSSD
NCN49597
PC20111019.2
TO Power Amplifier
FROM Line Coupler
TO Application
Micro Controller
TxD
RxD
T_REQ
BR0
BR1
CRC
TX_DATA / PRE_SLOT
5
VDD1V8
IO[9:3]
5
SPI I/F
5
Figure 7. S − FSK Modem NCN49597 Block Diagram
Transmitter
The NCN49597 Transmitter function block prepares the
communication signal which will be sent on the
transmission channel during the transmitting phase. This
block is connected to a power amplifier which injects the
output signal on the mains through a line
− coupler.
Receiver
The analog signal coming from the line − coupler is low
pass filtered in order to avoid aliasing during the conversion.
Then the level of the signal is automatically adapted by an
automatic gain control (AGC) block. This operation
maximizes the dynamic range of the incoming signal. The
signal is then converted to its digital representation using
sigma delta modulation. From then on, the processing of the
data is done in a digital way. By using dedicated hardware,
a direct quadrature demodulation is performed. The signal
demodulated in the base band is then low pass filtered to
reduce the noise and reject the image spectrum.
Clock and Control
According to the IEC 61334 − 5 − 1 standard, the frame data
is transmitted at the zero cross of the mains voltage. In order
to recover the information at the zero cross, a zero cross
detection of the mains is performed. A phase
− locked loop
(PLL) structure is used in order to allow a more reliable
reconstruction of the synchronization. This PLL permits as
well a safer implementation of the ”repetition with credit”
function (also known as chorus transmission). The clock
generator makes use of a precise quartz oscillator master.
The clock signals are then obtained by the use of a
programmed division scheme. The support circuits are also
contained in this block. The support circuits include the
necessary blocks to supply the references voltages for the
AD and DA converters, the biasing currents and power
supply sense cells to generate the right power off and startup
conditions.