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NB3L208KMNGEVB
Page 1: ...h a proper external VTH reference supply These signals will be translated to HCSL and eight identical copies of Clock will be distributed operating up to 350 MHz This manual should be used in conjunct...
Page 2: ...y during Phase Noise Testing VDD GND DIF_0 7 DIF_0 7 Power Supplies Each VDD VDD_0 VX on board GND_0 DUTGND on board and SMAGND power supply has a separate side launch banana jack located on bottom si...
Page 3: ...W 33 W 33 W 33 W 33 W 33 W 33 W 33 W 33 W 33 W 33 W 33 W SMAGND SMAGND R3 475 W R2 50 W R1 50 W C1 0 1 mF SMAGND SMAGND C2 0 1 mF C3 0 1 mF C5 0 1 mF C4 0 1 mF C6 10 mF VDD_0 OE _ 7 6 CLK_IN CLK_IN G...
Page 4: ...For phase noise test low noise generator is required to ensure the best additive RMS Phase jitter of the DUT 4 Connect the DIF_n DIF_n outputs to the appropriate oscilloscope channel The board does n...
Page 5: ...uit and specifically disclaims any and all liability including without limitation special consequential or incidental damages Typical parameters which may be provided in SCILLC data sheets and or spec...
Page 6: ...Mouser Electronics Authorized Distributor Click to View Pricing Inventory Delivery Lifecycle Information ON Semiconductor NB3L208KMNGEVB...
