ON Semiconductor ECLLQFP32EVB, User Manual

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ECLLQFP32EVB
http://onsemi.com
2
Figure 2. Bottom View of the 32 − lead LQFP Evaluation Board
Bottom View
Enlarged Bottom View
Figure 3. Evaluation Board Lay − up
LAY − UP DETAIL
4 LAYER
LAYER 1 (TOP SIDE) 1 OZ
ROGERS 4003 0.008 in
LAYER 2 (GROUND PLANE P1) 1 OZ
FR − 4 0.020 in
LAYER 3 (GROUND, VCC & VEE, PLANE P2) 1 OZ
FR − 4 0.025 in
LAYER 4 (BOTTOM SIDE) 1 OZ
SILKSCREEN (TOP SIDE)
0.062 $ 0.007
Board Layout
The 32 − lead LQFP evaluation board was designed to be
versatile and accommodate several different configurations.
The input, output, and power pin layout of the evaluation
board is shown in Figures 4 and 5. The evaluation board has
at least thirteen possible configurable options. Table 1, list
the devices and the relevant configuration that utilizes this
PCB board. Lists of components and simple schematics are
located in Figures 6 through 18. Place SMA connectors on
J1 through J32, 50
W
chip resistors between ground pad and
Pin 1 pad through Pin 32 pad, and chip capacitors C1 through
C5 according to configuration figures. (C4 and C5 are 0.01
m
F and C1, C2, and C3 are 0.1
Ăm
F); (See Figure 5).