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AP0100AT2L00XUGAH

GEVB

CONFIDENTIAL AND PROPRIETARY

NOT FOR PUBLIC RELEASE

www.onsemi.com

5

Table 1. JUMPERS AND HEADERS 

(continued)

Jumper/Header No.

Description

Pins

Jumper/Header Name

P38, P39

IO Expander U38

Setting

P39 Open,

P38 Closed (Default)

EEPROM Address Set to 0x48

P39 Open,

P38 Open

EEPROM Address Set to 0x4C

P39 Closed,

P38 Open

EEPROM Address Set to 0x44

P39 Closed,

P38 Closed

EEPROM Address Set to 0x40

P40

GPIO_DATA16

1

2 (Default)

Auto-Configuration Access

Open

JTAG/UART Access

P41

GPIO_DATA16

1

2 (Default)

Auto-Configuration Access

Open

JTAG/UART Access

P42

GPIO_DATA16

1

2 (Default)

Auto-Configuration Access

Open

JTAG/UART Access

P43

SP1_SDO/SDI

1

2 (Default)

Beagle SPI No Access to Sensor SPI

Open

Beagle SPI Access to Sensor SPI

P44
P44

SP1_SCLK/CS_N

1

2 (Default)

Beagle SPI No Access to Sensor SPI

Open

Beagle SPI Access to Sensor SPI

P45

SPI_SDI

Open (Default)

Data or GND; AP0100 in Flash/Host Mode

1

2

High Z; AP0100 in Auto-Config Mode

P47, P48, P59

Serial I

2

C EEPROM

Address

P47 Closed,

P48 Open,

P59 Open

EEPROM Address Set to 0xAA (Default)

P47 Closed,

P48 Open,

P59 Open

EEPROM Address Set to 0xA2

P47 Open,

P48 Closed,

P59 Open

EEPROM Address Set to 0xA6

P47 Open,

P48 Open,

P59 Open

EEPROM Address Set to 0xAE

P49

SEN_SCLK

2

3 (Default)

AP0100 Serial Control

1

2

Demo 2

×

 Serial Control

P50

SEN_SDATA

2

3 (Default)

AP0100 Serial Control

1

2

Demo 2

×

 Serial Control

P51

SEN_RST_OUT

2

3 (Default)

AP0100 Reset

1

2

Demo 2

×

 Reset

P52

BEAGLE_SCL

1

2 (Default)

Demo 2

×

 Accessed

2

3

Sensor Accessed

P53

BEAGLE_SDA

1

2 (Default)

Demo 2

×

 Accessed

2

3

Sensor Accessed

P54

1OE/2OE

1

2 (Default)

Enable Level Transistor U9

2

3

Disable Level Transistor U9

P56, P57, P58

Video Filter Selection

1

2 (Default)

Active Low Pass Filter

2

3

Discrete Low Pass Filter

SW7

RESET

N/A

When Pushed, 240 ms Reset Signal will be Sent to

AP0100 Chip

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Summary of Contents for AP0100AT

Page 1: ...nal Demo 2 Controlled MClk Two Wire Serial Interface Parallel Interface HiSPi High Speed Serial Pixel Interface ROHS Compliant Block Diagram Figure 2 Block Diagram of AP0100AT2L00XUGAH GEVB This docum...

Page 2: ...DI_BAR P5 SPI_SCLK CS_N P44 SPI Mem Sel P7 TEST_BAR P3 ON_LED P11 GPIO_DATA16 P37 P40 P41 P42 1OE 2OE P54 OSC XTAL Sel P22 P23 MCLK_IN P16 VDD P26 Video Filter Sel P56 P57 P58 GPIO1_LED P17 STANDBY P6...

Page 3: ...Header No Jumper Header Name Pins Description P3 TRST_BAR Open OTPM Programming Voltage Not Supplied 2 3 Default Set to Normal Mode P4 SADDR Open Set to Test Mode Open Analog Test 1 Header P5 SPI_SDI...

Page 4: ...er Supply 2 3 External Power Supply Connection P22 P23 Oscillator Xtal Selection P22 1 2 P23 Open Default Selects Oscillator as AP0100 Input Clock P22 2 3 P23 Closed Selects Crystal as AP0100 Input Cl...

Page 5: ...ault Data or GND AP0100 in Flash Host Mode 1 2 High Z AP0100 in Auto Config Mode P47 P48 P59 Serial I2C EEPROM Address P47 Closed P48 Open P59 Open EEPROM Address Set to 0xAA Default P47 Closed P48 Op...

Page 6: ...uctor 2 baseboard has a similar 26 pin connector and 13 pin connector which mate with J5 and J6 of the headboard The four mounting holes secure the baseboard and the headboard with spacers and screws...

Page 7: ...ivalent classification in a foreign jurisdiction or any devices intended for implantation in the human body You agree to indemnify defend and hold harmless onsemi its directors officers employees repr...

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