722
Auxiliary Area Allocations by Address
Appendix D
Read/Write Area (Set by User)
Addresses
Name
Function
Settings
Status
after
mode
change
Status at
startup
Write
timing
Related
Flags,
Settings
Word
Bits
A500
11
Ethernet
Communi-
cation Error
Clear Flag
Turn this bit ON to clear Ethernet
communication error (Ethernet com-
munication error flag turns OFF).
OFF to ON:
Clear
Retained
Cleared
---
A40 to
A44
A46.15
12
IOM Hold Bit Turn this bit ON to preserve the sta-
tus of the I/O Memory when shifting
from PROGRAM to RUN or MONI-
TOR mode or vice versa. The I/O
Memory includes the CIO Area,
Transition Flags, Timer Flags and
PVs, Index Registers, and Data Reg-
isters.
(If the status of the IOM Hold Bit itself
is preserved in the PLC Setup (IOM
Hold Bit Status), the status of the I/O
Memory Area will be retained when
the PLC is turned ON or power is
interrupted.)
ON: Retained
OFF: Not
retained
Retained
See
Function
column.
See
Function
column.
PLC
Setup
(IOM Hold
Bit Status
setting)
13
Forced Sta-
tus Hold Bit
Turn this bit ON to preserve the sta-
tus of bits that have been force-set or
force-reset when shifting from PRO-
GRAM to MONITOR mode or vice
versa. Bits that have been force-set
or force-reset will always return to
their default status when shifting to
RUN mode.
(If the status of the Forced Status
Hold Bit itself is preserved in the PLC
Setup (Forced Status Hold Bit Sta-
tus), the status of force-set and
force-reset bits will be retained when
the PLC is turned ON or power is
interrupted.)
ON: Retained
OFF: Not
retained
Retained
See
Function
column.
See
Function
column.
PLC
Setup
(Forced
Status
Hold Bit
Status
setting)
14
Error Log
Reset Bit
Turn this bit ON to reset the Error
Log Pointer (A300) to 00.
The contents of the Error Log Area
itself (A100 to A199) are not cleared.
(This bit is automatically reset to 0
after the Error Log Pointer is reset.)
OFF to ON:
Clear
Retained
Cleared
---
A100 to
A199,
A300
15
Output OFF
Bit
Turn this bit ON to turn OFF all out-
puts from the CPU Unit, and Special
I/O Units. The INH indicator on the
front of the CPU Unit will light while
this bit is ON.
(The status of the Output OFF Bit is
retained through power interrup-
tions.)
---
Retained
Retained
---
---
Summary of Contents for CP1L-EL20DR-D
Page 3: ...CP1L EL20D CP1L EM30D CP1L EM40D CP1L EL EM CPU Unit Operation Manual Produced July 2017...
Page 4: ...iv...
Page 10: ...x...
Page 22: ...xxii...
Page 34: ...xxxiv Software Licenses and Copyrights 7...
Page 192: ...158 Trial Operation and Debugging Section 5 3...
Page 250: ...216 Automatic Clock Adjustment and Specifying Servers by Host Name Section 6 7...
Page 666: ...632 Trouble Shooting Section 11 7...
Page 696: ...662 Standard Models Appendix A...
Page 805: ...771 Connections to Serial Communications Option Boards Appendix F Connecting to Unit...
Page 806: ...772 Connections to Serial Communications Option Boards Appendix F...
Page 836: ...802 PLC Setup Appendix G...
Page 838: ...804 TCP Status Transitions Appendix H...
Page 840: ...806 Ethernet Network Parameters Appendix I...
Page 842: ...808 Buffer Configuration CP1L EL EM Appendix J...
Page 844: ...810 Ethernet Specifications Appendix K...
Page 851: ...Index 817 work words 118 write protection 447...
Page 852: ...818 Index...
Page 854: ...820 Revision History...
Page 855: ......