Omron CJ1G-CPUxx, Instructions Manual

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1079
CS-series Instruction Execution Times and Number of Steps Section 4-1
Note 1. When a double-length operand is used, add 1 to the value shown in the
length column in the following table.
2. These instructions are not supported by CS1, CJ1, or CS1D CPU Units.
4-1-29 Block Programming Instructions
DISABLE
PERIPH-
ERAL SER-
VICING IOSP
(See note 2.) 287 --- 13.9 19.8 --- --- ---
ENABLE
PERIPH-
ERAL SER-
VICING IORS
(See note 2.) 288 --- 63.6 92.3 --- --- ---
Instruction Mnemonic Code Length
(steps)
(See note.)
ON execution time (
µ
s) Conditions
CPU6 @ H CPU4 @ H CPU6 @ CPU4 @
Instruction Mnemonic Code Length
(steps)
(See note.)
ON execution time (
µ
s) Conditions
CPU6
@
H CPU4
@
H CPU6
@
CPU4
@
BLOCK
PROGRAM
BEGIN BPRG 096 2 12.1 13.0 13.0 13.0 ---
BLOCK
PROGRAM
END BEND 801 1 9.6 12.3 13.1 13.1 ---
BLOCK
PROGRAM
PAUSE BPPS 811 2 10.6 12.3 14.9 14.9 ---
BLOCK
PROGRAM
RESTART BPRS 812 2 5.1 5.6 8.3 8.3 ---
CONDI-
TIONAL
BLOCK
EXIT (Execution
condition)
EXIT 806 1 10.0 11.3 12.9 12.9 EXIT condition
satisfied
4.0 4.9 7.3 7.3 EXIT condition
not satisfied
CONDI-
TIONAL
BLOCK
EXIT EXIT (bit
address) 806 2 6.8 13.5 16.3 16.3 EXIT condition
satisfied
4.7 7.2 10.7 10.7 EXIT condition
not satisfied
CONDI-
TIONAL
BLOCK
EXIT (NOT) EXIT NOT
(bit address) 806 2 12.4 14.0 16.8 16.8 EXIT condition
satisfied
7.1 7.6 11.2 11.2 EXIT condition
not satisfied
Branching IF (execu-
tion condi-
tion) 802 1 4.6 4.8 7.2 7.2 IF true
6.7 7.3 10.9 10.9 IF false
Branching IF (relay
number) 802 2 6.8 7.2 10.4 10.4 IF true
9.0 9.6 14.2 14.2 IF false
Branching
(NOT) IF NOT
(relay num-
ber) 802 2 7.1 7.6 10.9 10.9 IF true
9.2 10.1 14.7 14.7 IF false
Branching ELSE 803 1 6.2 6.7 9.9 9.9 IF true
6.8 7.7 11.2 11.2 IF false
Branching IEND 804 1 6.9 7.7 11.0 11.0 IF true
4.4 4.6 7.0 7.0 IF false