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OMAP5912 Multimedia Processor

Real-Time Clock and Split Power

Reference Guide

Literature Number: SPRU782A

March 2004

Summary of Contents for OMAP5912

Page 1: ...OMAP5912 Multimedia Processor Real Time Clock and Split Power Reference Guide Literature Number SPRU782A March 2004...

Page 2: ...ute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual pro...

Page 3: ...ternet at www ti com Tip Enter the literature number in the search box provided at www ti com OMAP5912 Multimedia Processor Device Overview and Architecture Reference Guide literature number SPRU748 i...

Page 4: ...r down modes and handles chip level wake up events In deep sleep mode this module is still active to monitor wake up events This book describes the ULPD module and outline architecture OMAP5912 Multim...

Page 5: ...3 2 DSP level 2 interrupt handler referenced as DSP interrupt level 2 0 can handle 16 interrupts OMAP5912 Multimedia Processor Peripheral Interconnects Reference Guide literature number SPRU758 descri...

Page 6: ...face Reference Guide lit erature number SPRU764 describes the display interface of the OMAP5912 multimedia processor J LCD module J LCD data conversion module J LED pulse generator J Display interface...

Page 7: ...PRU768 describes the VLYNQ of the OMAP5912 multimedia processor VLYNQ is a serial communications interface that enables the extension of an internal bus segment to one or more external physical device...

Page 8: ...to capture the memory transactions from four interfaces EMIFF EMIFS OCP T1 and OCP T2 This module is located in the OMAP3 2 traffic controller TC OMAP5912 Multimedia Processor Real Time Clock Referenc...

Page 9: ...wer 20 7 1 ABB Functions Incompatible With Split Power 20 7 2 ABB Functions Compatible With Split Power 21 7 3 ON to OFF Description 22 7 4 OFF to ON Description 23 8 Interrupt Management 23 8 1 Timer...

Page 10: ...in RESET_MODE 1 or RTC_CTRL_REG SPLIT_POWER 0 20 9 Startup With RTC_CTRL_REG SPLIT_POWER 1 for OMAP5912 RESET_MODE 0 21 10 ON to OFF With SPLIT POWER 1 for OMAP5912 RESET_MODE 0 22 11 OFF to ON With R...

Page 11: ...rved 34 12 Alarm Seconds Register ALARM_SECONDS_REG 34 13 Alarm Minutes Register ALARM_MINUTES_REG 34 14 Alarm Hours Register ALARM_HOURS_REG 35 15 Alarm Days Register ALARM_DAYS_REG 35 16 Alarm Month...

Page 12: ...ctions of RTC block are Time information seconds minutes hours directly in binary coded decimal BCD code Calendar information day month year day of the week directly in BCD code up to the year 2099 In...

Page 13: ...state in device equipment some active logic elements are supplied Those elements are the real time clock RTC and the 32 kHz oscillator OSC32K in the digital baseband DBB and the power on reset POR an...

Page 14: ...ct I O RESERWRON_CORE POWERDOWN 3 Internal Level Shifters Internal level shifters are library standard macrocells that interface two core domains powered with two different voltage supplies The cell c...

Page 15: ...wer supply of UC469 does not exist input signals A and AZ are ambiguous this cell does not have any through current and the output is set to 0 Figure 3 Internal Level Shifter Y A UC469 YZ Y A AZ PWRDN...

Page 16: ...nts and the ASIC core It also contains the UC469 and some logic The logic allows masking of the TIPB bus signals to avoid consumption of internal level shifters except in RTC accesses 4 2 Backup Block...

Page 17: ...6 1 Resets for OMAP5912 Device With Split Power Feature Enabled The RTC module and its internal real time counter are reset by PWRON_RESET during power up OMAP5912 ASIC gates are reset by PWRON_RESET_...

Page 18: ...with RTC_CTRL_REG SPLIT_POWER and the RTC alarm In OFF mode the IRQ_SET is set to 0 and only the IRQ_ALARM_EXT can generate an interrupt on the pin RTC_WAKE_INT With a device in ON state both IRQ_ALAR...

Page 19: ...SPLIT_POWER 7 Using Split Power 7 1 ABB Functions Incompatible With Split Power Do not use split power The power cannot be cut in the core Figure 8 OMAP5912 in RESET_MODE 1 or RTC_CTRL_REG SPLIT_POWE...

Page 20: ..._ON_NOFF RESPWRON_CORE CLK32K_CORE RESET_MODE 0 Figure 9 assumes that backup battery is already inserted only the RTC power domain is powered and that the RTC is isolated from the core RTC_ON_NOFF bal...

Page 21: ...ERDOWN Switch off event RESET_MODE_0 On a switch off event RTC_ON_NOFF is set to 0 The 32 kHz clock is not fed to OMAP5912 core anymore and PWRON_RESET_CORE is set to 0 to indicate that the device goe...

Page 22: ...d The DBB core is also supplied and reset by PWRON_RESET_CORE until RTC_ON_NOFF is set to 1 Then the isolation mode is inactive the ULPD state machine receives PWRON_RESET_CORE and the clock starts it...

Page 23: ...1 0 1 0 1 RTC_STATUS_REG 3 MIN 1 1 1 0 1 RTC_STATUS_REG 2 SEC 1 1 1 1 1 when this event is concurrent with programmed periodical period Figure 12 Periodic Interrupt 32766 32767 CLK_32kHz CPT_32kHz IRQ...

Page 24: ...hour period and load the compensation registers with the drift compensation value Autocompensation is enabled by the AUTO_COMP_EN bit in the RTC_CTRL register If the COMP_REG value is positive compens...

Page 25: ...7FFE 7FFF 7FFA Clk 32 kHz Timer counter Second update 2 cycles are added to current second 0000 10 Split Power Compatibility The RTC and the 32 kHz oscillator are the only elements that must be active...

Page 26: ...he STATUS register until BUSY is equal to zero From this time and for a time of 15 s the available access period the MPU can perform several accesses into the time and calendar registers and time and...

Page 27: ...e access period to prevent spurious interrupt The RTC_DISABLE bit of the CTRL register must be used only to completely disable the RTC function When this bit is set the 32 kHz clock is gated and the R...

Page 28: ...mation The MPU can write into time and calendar registers without stopping the RTC but in this case the MPU must read the status register to be sure that the RTC updating takes place in more than 15 s...

Page 29: ...ists the RTC registers The tables below describe the register bits The RTC register types are grouped as follows General registers Compensation registers Time and calendar alarm registers Time and cal...

Page 30: ...1 Time and Calendar Registers The time and calendar information is available in dedicated registers called time and calendar registers These register values are written in binary coded decimal BCD cod...

Page 31: ...ge is 0 to 9 R W 0000 Table 5 Minutes Register MINUTES_REG Base Address 0xFFFB 4800 Offset 0x04 Bit Name Function R W Reset 7 4 MIN1 2nd digit of minutes Range is 0 to 5 R W 0000 3 0 MIN0 1st digit of...

Page 32: ...gister MONTHS_REG Base Address 0xFFFB 4800 Offset 0x10 Bit Name Function R W Reset 7 4 MONTH1 2nd digit of months Range is 0 to 1 R W 0000 3 0 MONTH0 1st digit of months Range is 0 to 9 R W 0001 Usual...

Page 33: ...0 RESERVED Reserved Table 12 Alarm Seconds Register ALARM_SECONDS_REG Base Address 0xFFFB 4800 Offset 0x20 Bit Name Function R W Reset 7 4 ALARM_SEC1 2nd digit of seconds Range is 0 to 5 R W 0000 3 0...

Page 34: ...Base Address 0xFFFB 4800 Offset 0x2C Bit Name Function R W Reset 7 4 ALARM_DAY1 2nd digit for days Range is 0 to 3 R W 0000 3 0 ALARM_DAY0 1st digit for days Range is 0 to 9 R W 0001 Table 16 Alarm Mo...

Page 35: ...1 Set the 32 kHz counter with COMP_REG value R W 0 4 TEST_MODE 0 Functional mode 1 Test mode autocompensation is enabled when the 32 kHz counter reaches its end R W 0 3 MODE_12_24 0 24 hour mode 1 12...

Page 36: ...D_EVENT One day has occurred R 0 4 1H_EVENT One hour has occurred R 0 3 1M_EVENT One minute has occurred R 0 2 1S_EVENT One second has occurred R 0 1 RUN 0 RTC is frozen 1 RTC is running R 0 0 BUSY 0...

Page 37: ...hour 3 Every day R W 00 Note The MPU must respect the BUSY period to prevent spurious interrupt Table 21 RTC Compensation LSB Register RTC_COMP_LSB_REG Base Address 0xFFFB 4800 Offset 0x4C Bit Name Fu...

Page 38: ...e 32 kHz counter every hour R W 0x00 Table 23 RTC Oscillator Register RTC_OSC_REG Base Address 0xFFFB 4800 Offset 0x54 Bit Name Function R W Reset 4 OSC32K_PWRDN_R Control of 32 kHz oscillator power d...

Page 39: ...Real Time Clock RTC 40 SPRU782A...

Page 40: ...pensation 25 output control 17 registers 27 setting time and calendar information 29 split power 14 split power block 16 split power compatibility 26 using split power 20 related documentation from Te...

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