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OEC UroView
®
2800 Table/Generator Functional Block Diagrams
61
Periodic Maintenance
PCI BUS 0
Image Path in
Display Adapter PCB
P9
From Image Processor
U12
Latch
Left
Frame
Buffer
U26, U21,
U22, U23,
U24
Video Buffer
MAX499
U5
Left Monitor
Video TP10
P5
RAMDAC3
TVP3030
U4
LD_D0
to
LD_D7
Left_Pix_Data 0
to
Left_Pix_Data 7
L_Display_Data
75
U16
Latch
Right
Frame
Buffer
U31, U27,
U28, U29,
U30
Video Buffer
MAX499
U7
Right Monitor
Video TP15
P8
RAMDAC4
TVP3030
U9
RD_D0
to
RD_D7
RT_Pix_Data 0
to
RT_Pix_Data 7
R_Display_Data
75
U17
Latch
TV_Video
Control
U40
Video Buffer
MAX499
U6
P12
BT121
DAC
U32
AD_D0
to
AD_D7
AUX_Pix_Data 0
to
AUX_Pix_Data 7
DAC_VID DATA
75
Fast Scan Video
to Left Monitor
Fast Scan Video
to Right Monitor
Interlaced Video
to VCR
Display Adapter PCB
U43
PCI BUS
INTERFACE
Host Pentium CPU
PCI Slot 5
U36
Left Video
Control
U37
Right Video
Control
VCR Input
Video TP11
6B
6B
6C
1
The Display Adapter PCB produces a 75 hZ display rate.
1
1
+2.5V
+3.3V
+5V
-5V
Conf_Done
RFPGA_LED
LFPGA_LED
PLX_CS0
DS1
DS2
Conf_Done and PLX_CS0 LED's on DS1 lit during normal operation.
RFPGA_LED and LFPGA_LED blink occassionaly during normal operation.
2
2
Page 5 of 6
28IMAGEP.DS4
07/01
2800
GE OEC Training
g
Image Path in Display Adapter PCB