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Summary of Contents for BISON II

Page 2: ...this manual is for information only and is subject to change without notice REVISION 1 0 IBM IBM PC XT AT PC DOS MS DOS OS 2 INTEL AMI Pentium ARE THE TRADEMARKS OR REGISTERED TRADEMARKS OF THEIR RES...

Page 3: ...y from the receiver Move the computer away from the receiver Plug the computer into a different outlet so that computer and receiver are on different branch circuits Ensure that card slot covers are i...

Page 4: ...power make sure that all the connectors memory modules and add on cards are secured 3 After power is on wait for a minute The system BIOS are going through a self test during this period and nothing i...

Page 5: ...m 2 4 DRAM Subsystem 2 4 DRAM Configuration 2 6 Chapter 3 CONFIGURING THE SYSTEM Installing the Processor 3 1 Installing RAM Modules 3 2 Configuring the Cache Memory 3 3 Control of System Speed 3 4 Re...

Page 6: ...cess DMA 4 7 Real Time Clock and CMOS RAM 4 8 CMOS RAM Address Map 4 9 Real Time Clock Information 4 10 System Expansion Bus 4 11 Appendix A OPERATION AND MAINTENANCE Static Electricity A 1 Keeping Th...

Page 7: ...ications nowadays With the Pentium processor and 64 bit interleaved memory system it delivers the highest performance among the PC AT class machines that ever been ISA bus and VESA bus are incorporate...

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Page 9: ...66MHz CPU Speed Turbo normal speed I O Slot Six 16 bit ISA slots One 8 bit ISA slot Two VESA VL bus slots supporting one VL master Cache Internal cache inside Pentium 8K instruction cache 8K data cac...

Page 10: ...____ DRAM Supports 4 banks of 32 bit wide SIMM modules with 1MB 4MB or 16MB page mode DRAMs Supports DRAM configurations from 2MB to 64MB Two non cacheable regions for VL ISA bus masters DRAM post wri...

Page 11: ...e floating point instruction in one clock The branch prediction unit includes two prefech buffers one to prefetch code in a linear fashion and one to prefetch code according to the Branch Target Buffe...

Page 12: ...le or dual bank Dual bank is accessed in interleaved manner and it can support 3 2 2 2 burst read cycle DRAM Subsystem The memory controller is 64 bit wide and has the following features Hidden refres...

Page 13: ...the area F0000h FFFFFh can only be shadowed as a whole Video BIOS at C0000h C7FFFh can be cached in the external cache after shadowing Two DRAM control regions can be selected to adapt the bus masteri...

Page 14: ...________ DRAM CONFIGURATION Bank 0 Bank 1 bits Bank 2 Bank 3 bits Total bytes 256K x 64 2M 256K x 64 256K x 64 4M 256K x 64 1M x 64 10M 256K x 64 4M x 64 34M 1M x 64 8M 1M x 64 1M x 64 16M 1M x 64 4M...

Page 15: ...g or replacing any component Installing the processor Pentium is a 273 pin PGA device Make sure the pin 1 of Pentium with a notch at the corner is line up with the pin 1 of the socket Before installin...

Page 16: ...____ Installing RAM modules BISON II has four banks on board for SIMM modules Bank 0 and bank 1 must be installed first Make sure pin 1 of the SIMM module inserted near the power connector Lock it fir...

Page 17: ...unction The external cache is organized by single bank or dual banks with sizes of 64KB to 512KB Follow the tables below to configure the system Cache size JP6 JP23 JP22 JP21 JP20 JP19 64K 2 1 2 1 2 1...

Page 18: ...r slow speed and press Ctrl Alt and for fast speed RESET CMOS SETUP INFORMATION Sometimes the improper setting of system setup may make the system malfunction In this case turn off the power and set J...

Page 19: ...CONFIGURING THE SYSTEM _________________________________________________________________________...

Page 20: ...J1 Keyboard Connector JP1 Reset CMOS J10 J11 Power Supply Connector J9 External Battery Connector JP2 Display Selection JP6 Cache Size Selection JP19 JP23 Cache Size Selection JP20 Power LED 6 Ext Loc...

Page 21: ...There are several options which allows user to select by hardware switches JP2 Display Selection JP2 CLOSE CGA EGA VGA default OPEN Monochrome display JP24 Power good Selection PIN 1 2 Power good sign...

Page 22: ...conditions these connectors should be connected to the indicators and switches of the system unit The functions and the pin assignment of the connectors on the motherboard are listed below JP18 Speak...

Page 23: ...___________________ J20 Power LED Ext Lock Connector Pin Assignment 1 5 Vdc 2 Key 3 Ground 4 Keyboard inhibit 5 Ground J10 J11 Power Supply Connector Pin Assignment 1 POWERGOOD 2 5 Vdc 3 12 Vdc 4 12 V...

Page 24: ...CONFIGURING THE SYSTEM _________________________________________________________________________ 6 5 Vdc...

Page 25: ..._______________________________ J9 External Battery Connector Pin Assignment 1 Vdc 2 not used 3 Ground 4 Ground JP26 Cooling Fan Connector Pin Assignment 1 5Vdc 2 Ground J1 Keyboard Connector Pin Assi...

Page 26: ...CONFIGURING THE SYSTEM _________________________________________________________________________ THIS PAGE IS INTENTIONALLY LEFT BLANK...

Page 27: ...BISON II MEMORY MAPPING Address Range Function 000000 7FFFFF 000K 512K System Board Memory 512K 080000 09FFFF 512K 640K System Board Memory 128K 0A0000 0BFFFF 640K 768K Display Buffer 128K 0C0000 0DFF...

Page 28: ...roller 1 8237 020 03F Interrupt Controller 1 8259 Master 040 05F Timer 8254 060 06F Keyboard Controller 070 07F Real Time Clock NMI non maskable interrupt mask 080 09F DMA Page Register 74LS612 0A0 0B...

Page 29: ...ICE 1F0 1F8 Fixed Disk 200 207 Game I O 278 27F Parallel Printer Port 2 2F8 2FF Serial Port 2 300 31F Prototype Card 360 36F Reserved 378 37F Parallel Printer Port 1 380 38F SDLC bisynchronous 2 3A0 3...

Page 30: ...BISON II has three programmable timer counters controlled by Headland chipset and they are defined as channels 0 through 2 Channel 0 System Timer Gate 0 Tied on Clk in 0 1 190 Mhz OSC Clk out 0 8259 I...

Page 31: ...0 of port hex 61 PPI bit Clk in 2 1 190 Mhz OSC Clk out 2 Used to drive the speaker Note Channel 1 is programmed to generate a 15 micro second period signal The 8254 Timer Counters are treated by syst...

Page 32: ...Function Microprocessor NMI Parity or I O Channel Check Interrupt Controllers CTLR 1 CTLR 2 IRQ0 Timer Output 0 IRQ1 Keyboard Output Buffer Full IRQ2 Interrupt from CTLR 2 IRQ8 Real time Clock Interr...

Page 33: ...TECHNICAL INFORMATION _________________________________________________________________________...

Page 34: ...________ DIRECT MEMORY ACCESS DMA BISON II supports seven DMA channels Channel Function 0 Spare 8 bit transfer 1 SDLC 8 bit transfer 2 Floppy Disk 8 bit transfer 3 Spare 8 bit transfer 4 Cascade for D...

Page 35: ...el 1 0083 DMA Channel 2 0081 DMA Channel 3 0082 DMA Channel 5 008B DMA Channel 6 0089 DMA Channel 7 008A Refresh 008F REAL TIME CLOCK AND CMOS RAM Real time clock and CMOS RAM are contained on board R...

Page 36: ...s byte 10 Diskette drive type byte drives A and B 11 Reserved 12 Fixed disk type byte drives C and D 13 Reserved 14 Equipment byte 15 Low base memory byte 16 High base memory byte 17 Low expansion mem...

Page 37: ...ng table describes real time clock bytes and specifies their addresses Byte Function Address 0 Seconds 00 1 Second alarm 01 2 Minutes 02 3 Minute alarm 03 4 Hours 04 5 Hour alarm 05 6 Day of week 06 7...

Page 38: ...________________ SYSTEM EXPANSION BUS BISON II provides six 16 bit slots and two VL bus slots The I O channel supports I O address space from hex 100 to hex 3FF Selection of data access either 8 or 16...

Page 39: ...TECHNICAL INFORMATION _________________________________________________________________________ The following figure shows the pin numbering for I O channel connectors A side and B side...

Page 40: ...TECHNICAL INFORMATION _________________________________________________________________________ The following figure shows the pin numbering for I O channel connectors C side and D side...

Page 41: ...ctors I O Channel A Side I O Pin Signal Name I O A1 I O CH CK I A2 SD7 I O A3 SD6 I O A4 SD5 I O A5 SD4 I O A6 SD3 I O A7 SD2 I O A8 SD1 I O A9 SD0 I O A10 I O CH RDY I A11 AEN O A12 SA19 I O A13 SA18...

Page 42: ...TECHNICAL INFORMATION _________________________________________________________________________ A27 SA4 I O A28 SA3 I O A29 SA2 I O A30 SA1 I O A31 SA0 I O...

Page 43: ...GND Ground B2 RESET DRV I B3 5 Vdc Power B4 IRQ9 I B5 5 Vdc Power B6 DRQ2 I B7 12 Vdc Power B8 0WS I B9 12 Vdc Power B10 GND Ground B11 SMEMW O B12 SMEMR O B13 IOW I O B14 IOR I O B15 DACK3 I B16 DRQ...

Page 44: ...TECHNICAL INFORMATION _________________________________________________________________________ B29 5 Vdc Power B30 OSC O B31 GND Ground...

Page 45: ...______________ I O Channel C Side I O Pin Signal Name I O C1 SBHE I O C2 LA23 I O C3 LA22 I O C4 LA21 I O C5 LA20 I O C6 LA19 I O C7 LA18 I O C8 LA17 I O C9 MEMR I O C10 MEMW I O C11 SD8 I O C12 SD9 I...

Page 46: ..._________________ I O Channel D Side I O Pin Signal Name I O D1 MEM CS16 I D2 I O CS16 I D3 IRQ10 I D4 IRQ11 I D5 IRQ12 I D6 IRQ15 I D7 IRQ14 I D8 DACK0 O D9 DRQ0 I D10 DACK5 O D11 DRQ5 I D12 DACK6 O...

Page 47: ...wing table summery pin assignments for VESA VL bus connector VL bus side A I O Pin Signal Name A1 CD1 A2 CD3 A3 GROUND A4 CD5 A5 CD7 A6 CD9 A7 CD11 A8 CD13 A9 CD15 A10 GROUND A11 CD17 A12 POWER A13 CD...

Page 48: ...TECHNICAL INFORMATION _________________________________________________________________________ A25 CA24 A26 CA22 A27 POWER A28 CA20...

Page 49: ..._____ VL bus side A I O Pin Signal Name A29 CA18 A30 CA16 A31 CA14 A32 CA12 A33 CA10 A34 CA8 A35 GROUND A36 CA6 A37 CA4 A38 WBACK A39 BEO A40 POWER A41 BE1 A42 BE2 A43 GROUND A44 BE3 A45 ADS A46 LRDY...

Page 50: ..._______ VL bus side B I O Pin Signal Name B1 CD0 B2 CD2 B3 CD4 B4 CD6 B5 CD8 B6 GROUND B7 CD10 B8 CD12 B9 POWER B10 CD14 B11 CD16 B12 CD18 B13 CD20 B14 GROUND B15 CD22 B16 CD24 B17 CD26 B18 CD28 B19 C...

Page 51: ...___ VL bus side B I O Pin Signal Name B29 GROUND B30 CA17 B31 CA15 B32 POWER B33 CA13 B34 CA11 B35 CA9 B36 CA7 B37 CA5 B38 GROUND B39 CA3 B40 CA2 B41 n c B42 RESET B43 D C B44 M IO B45 W R B46 RDY B47...

Page 52: ...TECHNICAL INFORMATION _________________________________________________________________________...

Page 53: ...TECHNICAL INFORMATION _________________________________________________________________________ THIS PAGE IS INTENTIONALLY LEFT BLANK...

Page 54: ...en handling the add on card don t contact the components on the cards or their golden finger Hold the cards by their edges KEEPING THE SYSTEM COOL The motherboard contains many high speed components a...

Page 55: ...he contact between the golden finger and the slot may be poor and thus the add on card may not work properly Use a pencil eraser to clean the golden finger if dirt is found CLEANING THE MOTHERBOARD Th...

Page 56: ...d remove all SIMM modules Carefully place the modules back to the sockets and make sure that all the modules are locked by the locking latches firmly In some other cases the total memory found by the...

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