Count the number of flashes; the resulting number matches the POST error found
in the Table 18–2. For example, five flashes indicates the CPU test failed.
The POST codes are listed in numerical order. This is not the sequence in which
the actions are executed.
Table 18–1 POST port 80 codes
Port 80
Code
POST Routine Description
Start POST (BIOS is executing)
00h
Start CPU register test
01h
Start power-on delay
02h
Power-on delay finished
03h
Keyboard BAT finished
04h
Disable shadowing and cache
05h
Compute ROM CRC, wait for KBC
06h
CRC okay, KBC ready
07h
Verifying BAT command to KB
08h
Start KBC command
09h
Start KBC data
0Ah
Start pin 23, 24 blocking and unblocking
0Bh
Start KBC NOP command
0Ch
Test CMOS RAM shutdown register
0Dh
Check CMOS checksum
OEh
Initialize CMOC contents
0Fh
Initialize CMOS status for date/time
10h
Disable DMA, PICs
11h
Disable Port B, video display
12h
Initialize board, start memory detection
13h
Start timer tests
14h
Test 8254 T2, for speaker, Port B
15h
Test 8254 T1, for refresh
16h
Test 8254 T0, for 18.2 Hz
17h
Start memory refresh
18h
Test memory refresh
19h
Test 15
μ
sec ON/OFF time
1Ah
1Bh
Test base 64KB memory
1Ch
Test data lines
20h
Test address lines
21h
Test parity (toggling)
22h
Test Base 64KB memory
23h
Prepare system for IVT initialization
24h
Initialize vector table
25h
Read 8042 for turbo switch setting
26h
Initialize turbo data
27h
Modification of IVT
28h
Video in monochrome verified
29h
Video in color mode verified
2Ah
Toggle parity before video ROM test
2Bh
Initialize before video ROM test
98
