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TF
A9812_2
© NXP B
.V
. 2009. All r
ights reser
v
ed.
Preliminar
y data sheet
Re
v
. 02 — 22 Jan
uar
y 2009
5 of 66
NXP Semiconductor
s
TF
A9812
BTL stereo Class-D audio amplifier with I
2
S input
6.
Block diagram
Fig 1.
TFA9812 block diagram
15
16, 17
18, 19
10, 11
25
23, 24
26, 27
V
DDP
V
SSP1
22
BOOT1P
V
DDP
OUT1P
V
SSP2
BOOT1N
OUT1N
STAB1
BOOT2P
STAB1
CONTROL
LOGIC
20, 21
DRIVER
HIGH
12
13, 14
V
DDP
V
SSP2
V
DDP
OUT2P
V
SSP2
BOOT2N
OUT2N
STAB2
STAB2
XTALIN
XTALOUT
MCLK
REFERENCES
PROTECTION
OVP
UVP
OCP
OTP
ODP
WP
CDELAY
DIAG
1
2
47
31
39
41
42
4
5
TFA9812
010aaa217
CONTROL
LOGIC
DRIVER
HIGH
DRIVER
LOW
DRIVER
LOW
CONTROL
LOGIC
CONTROL
LOGIC
DRIVER
HIGH
DRIVER
LOW
DRIVER
HIGH
DRIVER
LOW
PWM
CONTROLLER
PWM
CONTROLLER
CONTROL
INTERFACE
REGISTER
ADDRESS
HEX 01
PHASED
LOCKED
LOOP
THERMAL
FOLDBACK
OSCILLATOR
ADC
1
0
34
35
36
37
38
POWERUP
SDA/MS
GAIN
33
ENABLE
CSEL
ADSEL2/PLIM2
ADSEL1/PLIM1
SCL/SFOR
STABD
REFD
STABA
REFA
30
29
48
8
EXPOSED DIE PADDLE V
SS1
V
SS2
46
45
44
BCK
WS
DATA
CSEL
TEST1
TEST2
AVOL
V
DDD(3V3)
V
DDA(3V3)
V
DDA
7
43
32
40
3
6
9
28
CLOCK
PROTECTION
LP
UFP
OFP
IBP
SERIAL
AUDIO
INTERFACE
10-BAND
PARAMETRIC
EQUALIZER
VOLUME
CONTROL
AND SOFT
MUTE
INTER-
POLATION
FILTER AND
DE-EMPHASIS
POWER
LIMITER
GAIN
