Chapter 4 Clock Description
MPC5602P Microcontroller Reference Manual, Rev. 4
86
Freescale Semiconductor
•
The Clock Monitoring Unit (CMU_0) monitors the clock frequency of the FMPLL_0 and the
XOSC signal against the IRC and provides clock out of range information about the monitored
clock signals.
•
FMPLL_0 provides a signal that indicates a loss of lock. Each loss of lock signal is sent to the CGM
module.
Upon the detection of one of the above mentioned failures, the MPC5602P device either asserts a reset,
generates an interrupt, or sends the device into the SAFE state.
The reaction to each of the clock failures and system parameters (like active clocks and SYS_CLK clock
source) that become active in SAFE state are under software control and can be configured in the ME
module.
4.6
IRC 16 MHz internal RC oscillator (RC_CTL)
The IRC output frequency can be trimmed using RCTRIM bits. After a power-on reset, the IRC is trimmed
using a factory test value stored in test flash memory. However, after a power-on reset the test flash
memory value is not visible at RC_CTL[RCTRIM], and this field shows a value of zero. Therefore, be
aware that the RC_CTL[RCTRIM] field does not reflect the current trim value until you have written to
it. Pay particular attention to this feature when you initiate a read-modify-write operation on RC_CTL,
because a RCTRIM value of zero may be unintentionally written back and this may alter the IRC
frequency. In this case, you should calibrate the IRC using the CMU.
In this oscillator, two's complement trimming method is implemented. So the trimming code increases
from -32 to 31. As the trimming code increases, the internal time constant increases and frequency reduces.
Please refer to device datasheet for average frequency variation of the trimming step.
Address: 0xC3FE_0060
(Base + 0x0000)
Access: Supervisor read/write; User read-only
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
RCTRIM[5:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 4-4. RC Control register (RC_CTL)
Table 4-1. RC_CTL field descriptions
Field
Description
RCTRIM[5:0]
Main RC trimming bits
