Chapter 20 Deserial Serial Peripheral Interface (DSPI)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
483
The following delay variables generate the same delay, or as close as possible, from the DSPI_100 MHz
system clock that a QSPI generates from a 40 MHz system clock. For other system clock frequencies, you
can recompute the values using the information presented in
Section 20.9.3, “Delay settings
.”
•
For BITSE = 0
8 bits per transfer.
•
For DT = 0
0.425 µs delay: for this value, the closest value in the DSPI is 0.480 µs.
•
For DSCK = 0
0.5 of the SCK period: for this value, the value for the DSPI is 20 ns.
20.9.5
Calculation of FIFO pointer addresses
The user has complete visibility of the TX and RX FIFO contents through the FIFO registers, and valid
entries can be identified through a memory mapped pointer and a memory mapped counter for each FIFO.
The pointer to the first-in entry in each FIFO is memory mapped. For the TX FIFO the first-in pointer is
the transmit next pointer (TXNXTPTR). For the RX FIFO the first-in pointer is the pop next pointer
(POPNXTPTR).
Refer to
Section 20.8.3.4, “Transmit First In First Out (TX FIFO) buffering mechanism
Section 20.8.3.5, “Receive First In First Out (RX FIFO) buffering mechanism
for details on the FIFO
operation. The TX FIFO is chosen for the illustration, but the concepts carry over to the RX FIFO.
illustrates the concept of first-in and last-in FIFO entries along with the FIFO counter.
Table 20-29. MPC5602P QSPI compatibility with the DSPI
MPC5602P family control bits
DSPI corresponding control bits
Corresponding DSPI
x
_CTAR register configuration
BITS
E
CTAS[0]
DT
CTAS[1
]
DSCK CTAS[2] DSPI
x
_CTAR
x
FMSZ
PDT
DT
PCSSC
K
CSSCK
0
0
0
0
0111
10
0011
00
0000
0
0
1
1
0111
10
0011
User
User
0
1
0
2
0111
User
1
1
Selected by user.
User
00
0000
0
1
1
3
0111
User
User
User
User
1
0
0
4
User
10
0011
00
0000
1
0
1
5
User
10
0011
User
User
1
1
0
6
User
User
User
00
0000
1
1
1
7
User
User
User
User
User
