Chapter 18 Enhanced Direct Memory Access (eDMA)
MPC5602P Microcontroller Reference Manual, Rev. 4
410
Freescale Semiconductor
This source read/destination write processing continues until the inner minor byte count has been
transferred. The eDMA Done Handshake signal is asserted at the end of the minor byte count transfer.
Figure 18-20. eDMA operation, part 2
After the inner minor byte count has been moved, the final phase of the basic data flow is performed. In
this segment, the address path logic performs the required updates to certain fields in the channel’s TCD:
for example., SADDR, DADDR, CITER. If the outer major iteration count is exhausted, then additional
operations are performed. These include the final address adjustments and reloading of the BITER field
into the CITER. Additionally, assertion of an optional interrupt request occurs at this time, as does a
possible fetch of a new TCD from memory using the scatter/gather address pointer included in the
descriptor. The updates to the TCD memory and the assertion of an interrupt request are shown in
.
Slav
e Interface
eDMA
eDMA Interrupt Request
System Bus
Program Model/
Slave Write Data
Slave Write Address
Bus Write Data
Slave Read Data
Bus Address
eDMA Engine
TCD0
TCD
n
– 1*
eDMA Peripheral
Bus Read Data
Channel Arbitration
Request
SRAM
Transfer Control Descriptor
(TCD)
SRAM
Data Path
Control
Address
Path
eDMA Done Handshake
*
n
= 16 channels
