Chapter 18 Enhanced Direct Memory Access (eDMA)
MPC5602P Microcontroller Reference Manual, Rev. 4
392
Freescale Semiconductor
18.5.2.5
eDMA Set Enable Request Register (EDMA_SERQR)
The EDMA_SERQR provides a simple memory-mapped mechanism to set a given bit in the
EDMA_ERQRL to enable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_ERQRL to be set. Setting bit 1 (SERQ
n
) provides a global set
function, forcing the entire contents of EDMA_ERQRL to be asserted. Reads of this register return all
zeroes.
18.5.2.6
eDMA Clear Enable Request Register (EDMA_CERQR)
The EDMA_CERQR provides a simple memory-mapped mechanism to clear a given bit in the
EDMA_ERQRL to disable the DMA request for a given channel. The data value on a register write causes
the corresponding bit in the EDMA_ERQRL to be cleared. Setting bit 1 (CERQ
n
) provides a global clear
function, forcing the entire contents of the EDMA_ERQRL to be zeroed, disabling all DMA request
inputs. Reads of this register return all zeroes.
Address: Base + 0x0018
Access: User write-only
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
SERQ[0:6]
Reset
0
0
0
0
0
0
0
0
Figure 18-6. eDMA Set Enable Request Register (EDMA_SERQR)
Table 18-6. EDMA_SERQR field descriptions
Field
Descriptions
0
Reserved.
1–7
SERQ[0:6]
Set enable request.
0–15 Set corresponding bit in EDMA_ERQRL
16–63Reserved
64–127Set all bits in EDMA_ERQRL
Note:
Bit 2 (SERQ1) is not used.
Address: Base + 0x0019
Access: User write-only
0
1
2
3
4
5
6
7
R
0
0
0
0
0
0
0
0
W
CERQ[0:6]
Reset
0
0
0
0
0
0
0
0
Figure 18-7. eDMA Clear Enable Request Register (EDMA_CERQR)
