Chapter 11 System Integration Unit Lite (SIUL)
MPC5602P Microcontroller Reference Manual, Rev. 4
Freescale Semiconductor
257
11.5.2.15 Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24])
These registers configure the filter counter associated with each digital glitch filter.
11.5.2.16 Interrupt Filter Clock Prescaler Register (IFCPR)
This register configures a clock prescaler that selects the clock for all digital filter counters in the SIUL.
Table 11-19. MPGPDO[0:6] field descriptions
Field
Description
MASK[
x
]
[15:0]
Mask Field
Each bit corresponds to one data bit in the MPPDO[x] field at the same bit location.
0: The associated bit value in the MPPDO[
x
] field is ignored.
1: The associated bit value in the MPPDO[
x
] field is written.
MPPDO[
x
]
[15:0]
Masked Parallel Pad Data Out
Write the data register that stores the value to be driven on the pad in output mode.
Accesses to this register location are coherent with accesses to the bit-wise GPIO Pad Data
Output registers 0_3–68_71 (GPDO[0_3:68_71]).
The x and bit index define which MPPDO register bit is equivalent to which PDO register bit
according to the following equation:
MPPDO[
x
][
y
] = PDO[(
x
* 16) +
y
]
Address: Base + 0x1000 (IFMC0)
...
Base + 0x1060 (IFMC24) 25 registers
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
0
0
MAXCNT
x
[3:0]
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
Figure 11-17. Interrupt Filter Maximum Counter registers 0–24 (IFMC[0:24])
Table 11-20. IFMC[0:24] field descriptions
Field
Description
MAXCNT
x
[3:0]
Maximum Interrupt Filter Counter setting.
Filter Period = (T
CK
× MAXCNT
x)
+ (
n
× T
CK
)
Where
n
can be –2 to 3
MAXCNT
x
can be 0 to 15
T
CK
: Prescaled Filter Clock Period, which is IRC clock prescaled to IFCP value
T
IRC
: Basic Filter Clock Period: 62.5 ns (f
IRC
= 16 MHz)
