NXP Semiconductors QorIQ LS1028A, Reference Manual, Page: 58 / 112

Chapter 4
Qixis Programming Model
This chapter describes the contents of the register block (the BCSR - Board Control / Status Registers). These are contained
within the system controller FPGA or CPLD, and may be used to control and monitor the target system. These registers are
accessible over one or more system-specific interfaces, typically I2C, JTAG or an embedded processor. Refer to the system
reference manual for these connection details. In all cases, each interface will use the 12-bit base address supplied in the
definitions below.
This table shows the register memory map for Qixis.
Table 35. Qixis Register Memory Map
Offset Register
Width
(In bits)
Access Reset value
000h
Identification (ID) 8 RO 01000111b
001h
Board Version (VER) 8 RO 00010001b
002h
Qixis Version (QVER) 8 RO 00000001b
003h
Programming Model (MODEL) 8 RO 01000000b
004h
Minor Revision (MINOR) 8 RW 00000101b
005h
General Control (CTL) 8 RW 00000000b
006h
Auxiliary (AUX) 8 RW 00000000b
009h
System Status (STAT_SYS) 8 RO 00000000b
00Ah
Alarm (ALARM) 8 RO 00000000b
00Bh
Presence Detect 1 (STAT_PRES1) 8 RO 0110xxxxb
00Ch
Presence Detect 2 (STAT_PRES2) 8 RO xxxx1111b
00Eh
LED Control (LED) 8 RW 00000000b
010h
Reconfiguration Control (RCFG) 8 RW 0001x00xb
01Dh
USB Control (USB_STAT) 8 RW 00000001b
01Eh
USB Control (USB_CTL) 8 RW 00xx0000b
01Fh
Watchdog (WATCH) 8 RW xxxxxxxb
021h
Power Control 2 (PWR_CTL2) 8 RW 00000000b
024h
Power Status 0 (PWR_MSTAT) 8 RO 110010xxb
Table continues on the next page...
Qixis Programming Model
QorIQ LS1028A Reference Design Board Reference Manual, Rev. b, 11/2018
58
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