NXP Semiconductors QN902 Series, User Manual

Page: 26 / 128

NXP Semiconductors
QN902x
User Manual of QN902x
UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User Manual Rev 1.3
— 05 November 2018
26 of 128
25 RW 0 LO_ICPH Reserve d. Write ‘0’
24-23 RW 01b LO_BM_FIL[1-0] Reserved. Write ‘0 1b ’
22-21 RW 01b LO_BM_DAC[1-
0] Reserved. Write ‘0 1b ’
20-19 RW 01b LO_BM_CML_C[
1-0] Reserved. Write ‘0 1b ’
18-17 RW 01b LO_BM_CML_D
[1-0] Reserved. Write ‘0 1b ’
16-15 RW 01b LO_BM_BVCO[1
-0] Reser ved. Write ‘0 1b ’
14-12 RW 100b LO_VCO_AMP[2
-0] Reserved. Write ‘ 100b ’
11 RW 0 PMUX_EN Reserved. Write ‘0’
10-9 RW 0 PA_PHASE[1-0] Reserved. Write ‘0’
8 RW 0 DAC_TEST_EN Reserved. Write ‘0’
7-0 RW 0 DAC_TEST[7-0] Reserved. Write ‘0’
Table 25 ADCCR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R
SVD
SPE
ED_UP_T
IM
E[7
]
SPE
ED_UP_T
IM
E[6
]
SPE
ED_UP_T
IM
E[5
]
SPE
ED_UP_T
IM
E[4
]
SPE
ED_UP_T
IM
E[3
]
SPE
ED_UP_T
IM
E[2
]
SPE
ED_UP_T
IM
E[1
]
SPE
ED_UP_T
IM
E[0
]
R
SVD
CK
_DAC
_DL
Y
BY
PA
SS
_T
ES
TBUF
SEL_T
ES
T_E
N
TES
TR
EG[7]
TES
TR
EG[6]
TES
TR
EG[5]
TES
TR
EG[4]
TES
TR
EG[3]
TES
TR
EG[2]
TES
TR
EG[1]
TES
TR
EG[0]
R
SVD
A
D
C
_DI
G_R
ST
A
D
C
_C
LK_S
EL
A
D
C
_DI
V_BY
PA
SS
A
D
C
_DI
V
[3]
A
D
C
_DI
V
[2]
A
D
C
_DI
V
[1]
A
D
C
_DI
V
[0]
1 0 1 0 1 1 1 0 1 1 1 1 0 0 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 1 1
W W W W
RW RW RW RW RW RW RW RW
R
RW RW RW RW RW RW RW RW RW RW RW
R
RW RW RW RW RW RW RW
Bit Type Reset Symbol Description
31-28 R 0 RSVD Reserved
27-20 RW 11101111b SPEED_UP_TIM
E[7-0] Reserved , write ‘ 11101111b ’
19 R 0 RSVD Reserved
18 RW 0 CK_DAC_DLY Reserved
17
RW
1
BYPASS_TESTBU
F Reserved
16 RW 0 SEL_TEST_EN Reserved
15-8 RW 0 TESTREG[7-0] Reserved
7 R 0 RSVD Reserved
6 RW 1 ADC_DIG_RST 0 = Reset SAR ADC digital Interface;
5 RW 0 ADC_CLK_SEL Select ADC source Clock
0 = 16MHz, 1: 32KHz
4 RW 0 ADC_DIV_BYPA
SS ‘1’ is bypass ADC Divider;
3-0 RW 0111b ADC_DIV[3-0] If ADC_DIV_BYPASS is ‘0’,