NXP Semiconductors
QN902x
User Manual of QN902x
UM10996
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2018. All rights reserved.
User Manual
Rev 1.3
— 05 November 2018
11 of 128
31-
30
RW
01b
CLK_MUX[1-0]
Select system clock source.
00b = High frequency crystal 16MHz or 32MHz;
01b = 20MHz internal high frequency;
10b = 32MHz PLL output;
11b = 32KHz low speed clock;
29
RW
0
SEL_CLK_32K
1 = Select 32KHz clock from RCO
0 = Select 32KHz clock from XTAL32
28
RW
1
BLE_FRQ_SEL
Describe BLE clock frequency.
0 = 8 MHz;
1 = 16 MHz
27
RW
1
BLE_DIV_BYPASS
‘1’ is bypass BLE Divider; Only 16 or 8 MHz are supported;
26
RW
0
BLE_DIVIDER
If BLE_DIV_BYPASS is ‘0’,
BLE_CLK = AHB_CLK / (2*(BLE_D1));
Only 16 or 8 MHz are supported;
25
RW
1
AHB_DIV_BYPASS
‘1’ is bypass AHB Divider;
24-
16
RW
0
AHB_DIVIDER[8-0]
If AHB_DIV_BYPASS is ‘0’,
AHB_CLK = SYS_CLK/(2*(APB_1));
15
RW
0
USART1_DIV_BYPASS
‘1’ is bypass USART1 Divider;
14-
12
RW
001b
USART1_DIVIDER[2-
0]
If USART1_DIV_BYPASS is ‘0’,
USART1_CLK = AHB_CLK/(2*(USART1_1))
11
RW
1
USART0_DIV_BYPASS
‘1’ is bypass USART0 Divider;
10-
8
RW
0
USART0_DIVIDER[2-
0]
If USART0_DIV_BYPASS is ‘0’,
USART0_CLK = AHB_CLK/(2*(USART1_1))
7
R
0
RSVD
Reserved
6
RW
0
APB_DIV_BYPASS
‘1’ is bypass APB Divider;
5-4
RW
01b
APB_DIVIDER[1-0]
If APB_DIV_BYPASS is ‘0’,
APB_CLK = AHB_CLK/(2*(APB_1))
3
RW
1
TIMER_DIV_BYPASS
‘1’ is bypass TIMER Divider;
2-0
RW
001b
TIMER_DIVIDER[2-0]
If TIMER_DIV_BYPASS is ‘0’,
TIMER_CLK = AHB_CLK / (2*(TIMER_D 1));
Table 6 STCR (SYS_TICK_CTRL)
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
ST
C
LEN
R
SVD
R
SVD
R
SVD
R
SVD
R
SVD
STC
A
LIB
1
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
1
0
0
0
1
1
1
RW
R
R
R
R
R
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
Bit
Type
Reset
Symbol
Description
31
RW
1
STCLEN
‘1’ is enable STCLKEN, so that SCLK of CP
U can be gated by
STCLKEN;
30-26
R
00000
RSVD
Reserved
