NXP Semiconductors QN902 Series, User Manual

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NXP Semiconductors
QN902x
User Manual of QN902x
UM10996 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2018. All rights reserved.
User Manual Rev 1.3
— 05 November 2018
10 of 128
20 W1 x NGATING_ADC Write 1 to enable ADC clock
19 W1 x NGATING_DMA Write 1 to enable DMA clock
18 W1 x NGATING_BLE_AHB Write 1 to enable BLE AHB clock
17 W1 x NGATING_PWM Write 1 to enable PWM clock
16 x RSVD Reserved
15 W1 x DIS_LOCKUP_RST Write 1 to disable LOCKUP reset control
14 W1 x CLR_BLE_RST Write 1 to clear BLE reset
13 W1 x CLR_DP_RST Write 1 to clear datapath reset
12 W1 x CLR_DPREG_RST Write 1 to clear datapath register reset
11 W1 x CLR_SLPTIM_RST Write 1 to clear sleep timer reset
10 W1 x CLR_I2C_RST Write 1 to clear I2C reset
9 W1 x CLR_GPIO_RST Write 1 to clear GPIO reset
8 W1 x CLR_WDOG_RST Write 1 to clear Watch Dog reset
7 W1 x CLR_TIMER3_RST Write 1 to clear timer 3 reset
6 W1 x CLR_TIMER2_RST Write 1 to clear timer 2 reset
5 W1 x CLR_TIMER1_RST Write 1 to clear timer 1 reset
4 W1 x CLR_TIMER0_RST Write 1 to clear timer 0 reset
3 W1 x CLR_USART1_RST Write 1 to clear USART1 (SPI 1 and UART 1) reset
2 W1 x CLR_USART0_RST Write 1 to clear USART0 (SPI 0 and UART 0) reset
1 W1 x CLR_DMA_RST Write 1 to clear DMA reset
0 W1 x CLR _CPU_RST Write 1 to clear CPU reset
Table 5 CMDCR (CLK_MUX_DIV_CTRL)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10
9 8 7 6 5 4 3 2 1 0
C
LK_M
U
X[1]
C
LK_M
U
X[0]
SEL_C
LK_32
K
BLE_
FR
Q_
SEL
BLE_
D
IV_BY
PA
SS
BLE_
D
IVI
D
ER
A
HB_DI
V_BY
PA
SS
A
HB_DI
V
ID
ER
U
SA
R
T1_
D
IV
_B
YPA
SS
U
SA
R
T1_
D
IV
ID
ER
U
SA
R
T0_
D
IV
_B
YPA
SS
U
SA
R
T0_
D
IV
ID
ER
R
SVD
A
PB
_DI
V_BY
PA
SS
A
PB
_DI
VI
D
ER
TIM
ER
_DI
V_BY
PA
SS
TIM
ER
_DI
VI
D
ER
0 1 0 1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 1 1 0 0 1
RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW
R
RW RW RW RW RW RW RW
Bit Type Reset Symbol Description