NXP Semiconductors PXN2020, Reference Manual, Page: 961 / 1376

Deserial – Serial Peripheral Interface (DSPI)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 30-35
30.4.3.5.2 Draining the RX FIFO
Host software or the eDMA controller can remove (pop) entries from the RX FIFO by reading the DSPI
POP RX FIFO Register (DSPI_POPR). For more information on DSPI_POPR, refer to
Section 30.3.2.7,
DSPI POP RX FIFO Register (DSPI_POPR). A read of the DSPI_POPR decrements the RX FIFO counter
by one. Attempts to pop data from an empty RX FIFO are ignored, and the RX FIFO counter remains
unchanged. The data returned from reading an empty RX FIFO is undetermined.
When the RX FIFO is not empty, the RX FIFO drain flag (RFDF) in the DSPI_SR is set. The RFDF bit is
cleared when the RX_FIFO is empty and the DMA controller indicates that a read from DSPI_POPR is
complete or by host software writing a 1 to the RFDF.
30.4.4 Deserial Serial Interface (DSI) Configuration
The DSI configuration supports pin-count reduction by serializing parallel input signals or register bits and
shifting them out in a SPI-like protocol. The timing and transfer protocol is described in
Section 30.4.8,
Transfer Formats. The received serial frames are converted to a parallel form (deserialized) and placed on
the parallel output signals or in a register.
The various features of the DSI configuration are set in the DSPI_DSICR. For more information on the
DSPI_DSICR, refer to
Section 30.3.2.10, DSPI DSI Configuration Register (DSPI_DSICR). The DSPI is
in DSI configuration when the DCONF field in the DSPI_MCR = 0b01.
The DSI frames can be from 4 to 16 bits long, but 4 to 32 bits can be used in the TSB configuration (see
Section 30.4.10, Timed Serial Bus (TSB), for detailed information).
30.4.4.1 DSI Master Mode
In DSI master mode, the DSPI initiates and controls the DSI transfers. The DSI master has these conditions
that can initiate a transfer:
• Continuous
• Change in data
The two transfer initiation conditions are described in Section 30.4.4.5, DSI Transfer Initiation Control.
Transfer attributes are set during initialization. The DSICTAS field in the DSPI_DSICR determines which
DSPI_CTAR
n register controls the transfer attributes.
30.4.4.2 DSI Slave Mode
In DSI slave mode, the DSPI responds to transfers initiated by a SPI or DSI bus master. In this mode the
DSPI does not initiate DSI transfers. Certain transfer attributes such as clock polarity and phase must be
set for successful communication with a DSI master. The DSI slave mode transfer attributes are set in the
DSPI_CTAR1.
30.4.4.3 DSI Serialization
In the DSI configuration, 4 to 16 bits can be serialized using two different sources. The TXSS bit in the
DSPI_DSICR selects between the DSPI DSI Serialization Data Register (DSPI_SDR) and the DSPI DSI