NXP Semiconductors PXN2020, Reference Manual, Page: 924 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-40 Freescale Semiconductor
The other two interrupt sources (bus off/transmit warning/receive warning and error) generate interrupts
like the MB interrupt sources, and can be read from CAN
x _ESR. The bus off/transmit warning/receive
warning and error interrupt mask bits are located in the CAN x _CTRL.
29.4.10 Bus Interface
The CPU access to FlexCAN registers are subject to the following rules:
• Read and write access to unimplemented or reserved address space results in access error. Any
access to unimplemented MB Rx individual mask register locations results in access error. Any
access to the Rx individual mask register space when the BCC bit in CAN
x _MCR is negated results
in access error.
• For a FlexCAN configuration that uses less than the total number of MBs and MAXMB is set
accordingly, the remaining MB and Rx mask register spaces can be used as general-purpose RAM
space. Note that the Rx individual mask registers can only be accessed in freeze mode, and this is
still true for unused space within this memory. Note also that reserved words within RAM cannot
be used. As an example, suppose FlexCAN is configured with 64 MBs and MAXMB is
programmed with zero. The maximum number of MBs in this case becomes one. The MB memory
starts at 0x0060, but the space from 0x0060 to 0x007F is reserved (for SMB usage), and the space
from 0x0080 to 0x008F is used by the one MB. This leaves us with the available space from
0x0090 to 0x047F. The available memory in the mask registers space would be from 0x0884 to
0x097F. Byte, word, and long word accesses are allowed to the unused MB space.
NOTE
Unused MB space must not be used as general purpose RAM while
FlexCAN is transmitting and receiving CAN frames.
29.5 Initialization and Application Information
This section provides instructions for initializing the FlexCAN module.
29.5.1 FlexCAN Initialization Sequence
The FlexCAN module can be reset in three ways:
• MCU-level hard reset, which resets all memory-mapped registers asynchronously
• MCU-level soft reset, which resets some of the memory-mapped registers synchronously (refer to
Table 29-7 to see what registers are affected by soft reset)
• SOFT_RST bit in CAN x _MCR, which has the same effect as the MCU level soft reset
Soft reset is synchronous and has to follow an internal request/acknowledge procedure across clock
domains. Therefore, it may take some time to fully propagate its effects. The SOFT_RST bit remains
asserted while soft reset is pending, so software can poll this bit to know when the reset has completed.
After the module is enabled (CAN x _MCR[MDIS] bit negated), FlexCAN must be put into freeze mode
before doing any configuration. In freeze mode, FlexCAN is un-synchronized to the CAN bus, the HALT
and FRZ bits in CAN
x _MCR are set, the internal state machines are disabled and the FRZ_ACK and