NXP Semiconductors PXN2020, Reference Manual, Page: 923 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-39
After requesting freeze mode, the user must wait for the FRZ_ACK bit to be asserted in CAN x _MCR
before executing any other action, otherwise FlexCAN can operate in an unpredictable way. In freeze
mode, all memory mapped registers are accessible.
Exiting freeze mode is done in one of these ways:
• CPU negates the FRZ bit in the CAN x _MCR
• The MCU exits debug mode and/or the HALT bit is negated
After it is out of freeze mode, FlexCAN tries to resynchronize to the CAN bus by waiting for
11 consecutive recessive bits.
29.4.8.2 Module Disabled Mode
This low-power mode is entered when the CAN x _MCR[MDIS] bit is asserted. If the module is disabled
during freeze mode, it shuts down the clocks to the CPI and MBM sub-modules, sets the
CAN
x _MCR[LPM_ACK] bit, and negates the CAN x _MCR[FRZ_ACK] bit. If the module is disabled
during transmission or reception, FlexCAN does the following:
• Waits to be in either idle or bus off state, or else waits for the third bit of intermission and then
checks it to be recessive
• Waits for all internal activities like move in or move out to finish
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the CPI and MBM sub-modules
• Sets the NOT_RDY and LPM_ACK bits in CAN x _MCR
The bus interface unit continues to operate, enabling the CPU to access memory mapped registers except
the free-running timer, the CAN
x _ECR and the message buffers, which cannot be accessed when the
module is disabled. Exiting from this mode is done by negating the CAN x _MCR[MDIS] bit, which
resumes the clocks and negates the CAN x _MCR[LPM_ACK] bit.
29.4.9 Interrupts
The FlexCAN module interrupts are ORed together at the chip level as described in Chapter 10, Interrupts
and Interrupt Controller (INTC).
There is an interrupt source for each MB from MB0 to MB15. There is no distinction between Tx and Rx
interrupts for a particular buffer, under the assumption that the buffer is initialized for either transmission
or reception. Each of the buffers has assigned a flag bit in the CAN
x _IFLAG2 or CAN x _IFLAG1 registers.
The bit is set when the corresponding buffer completes a successful transmission/reception and is cleared
when the CPU writes it to 1.
A combined interrupt for each of two MB groups, MB16–MB31 and MB32–MB63, is also generated by
an OR of all the interrupt sources from the associated MBs. This interrupt gets generated when any of the
MBs generates an interrupt. In this case the CPU must read the CAN
x_ IFLAG2 and CAN x_ IFLAG1
registers to determine which MB caused the interrupt.