NXP Semiconductors PXN2020, Reference Manual, Page: 910 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-26 Freescale Semiconductor
29.3.4.11 Rx Individual Mask Registers (CANx_RXIMR0
–
CANx_RXIMR63)
These registers are used as acceptance masks for ID filtering in Rx MBs and the FIFO. If the FIFO is not
enabled, one mask register is provided for each available message buffer, providing ID masking capability
on a per message buffer basis. When the FIFO is enabled (FEN bit in CAN
x _MCR is set), the first eight
mask registers apply to the eight elements of the FIFO filter table (on a one-to-one correspondence), while
the rest of the registers apply to the regular MBs, starting from MB8.
The individual Rx mask registers are implemented in RAM, so they are not affected by reset and must be
explicitly initialized prior to any reception. Furthermore, they can only be accessed by the CPU while the
module is in freeze mode. Out of freeze mode, write accesses are blocked and read accesses return all
zeros. Furthermore, if the BCC bit in the register is negated, any read or write operation to these registers
results in access error.
Table 29-15. CANx_IFLAG1 Field Descriptions
Field Description
BUF31I–
BUF8I
Message Buffer n Interrupt. Each bit represents the respective FlexCAN message buffer (MB31 to MB8) interrupt.
Write 1 to clear.
0 No such occurrence.
1 The corresponding buffer has successfully completed transmission or reception.
BUF7I Buffer MB7 Interrupt or “FIFO Overflow”
If the FIFO is not enabled, this bit flags the interrupt for MB7. If the FIFO is enabled, this flag indicates an overflow
condition in the FIFO (frame lost because FIFO is full).
0 No such occurrence.
1 MB7 completed transmission/reception or FIFO overflow.
BUF6I Buffer MB6 Interrupt or “FIFO Warning”
If the FIFO is not enabled, this bit flags the interrupt for MB6. If the FIFO is enabled, this flag indicates that 5 out
of 6 buffers of the FIFO are already occupied (FIFO almost full).
0 No such occurrence.
1 MB6 completed transmission/reception or FIFO almost full.
BUF5I Buffer MB5 Interrupt or “Frames Available in FIFO”
If the FIFO is not enabled, this bit flags the interrupt for MB5. If the FIFO is enabled, this flag indicates that at least
one frame is available to be read from the FIFO.
0 No such occurrence.
1 MB5 completed transmission/reception or frames available in the FIFO.
BUF4I–
BUF0I
Buffer MBn Interrupt or “Reserved”
If the FIFO is not enabled, these bits flag the interrupts for MB0 to MB4. If the FIFO is enabled, these flags are
not used and must be considered as reserved locations.
0 No such occurrence.
1 Corresponding MB completed transmission/reception.