NXP Semiconductors PXN2020, Reference Manual, Page: 888 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
29-4 Freescale Semiconductor
29.1.3.3 Listen-Only Mode
In this mode, transmission is disabled, all error counters are frozen, and the module operates in a CAN
error passive mode. Only messages acknowledged by another CAN station are received. If FlexCAN
detects a message that has not been acknowledged, it flags a BIT0 error (without changing the REC), as if
it was trying to acknowledge the message.
29.1.3.4 Loop-Back Mode
The module enters this mode when the LPB bit in the control register is asserted. In this mode, FlexCAN
performs an internal loop back that can be used for self test operation. The bit stream output of the
transmitter is internally fed back to the receiver input. The Rx CAN input pin is ignored and the Tx CAN
output goes to the recessive state (logic 1). FlexCAN behaves as it normally does when transmitting, and
treats its own transmitted message as a message received from a remote node. In this mode, FlexCAN
ignores the bit sent during the ACK slot in the CAN frame acknowledge field to ensure proper reception
of its own message. Transmit and receive interrupts are generated.
29.1.3.5 Module-Disabled Mode
This low-power mode is entered when the MDIS bit in the CAN x _MCR register is asserted. When
disabled, the clocks to the CAN protocol interface and message buffer management sub-modules are shut
down. Exit from this mode is done by negating the MDIS bit in the CAN
x _MCR register.
29.1.3.6 Halt Mode
This low power mode is entered when the corresponding HLT bit in the SIU_HLT0 is asserted. The HLT
bit drives the stop input to the module. When in halt mode, the module puts itself in an inactive state and
then informs the CPU that its clock can be shut down.
Exit from this mode happens when the HLT bit is de-asserted.
29.2 External Signal Description
Please refer to Table 3-1 and Section 3.4, Detailed Signal Description, for a complete description of the
FlexCAN signals.
29.3 Memory Map and Registers
This section provides a detailed description of all FlexCAN registers.
29.3.1 Module Memory Map
The complete memory map for an individual FlexCAN module is shown in Table 29-1 . Except for the base
addresses, all FlexCAN modules have identical memory maps.
The Rx global mask (CAN x _RXGMASK), Rx buffer 14 mask (CAN x _RX14MASK) and the Rx buffer
15 mask (CAN x _RX15MASK) registers are provided for backwards compatibility, and are not used when
the BCC bit in CAN x _MCR is asserted.