NXP Semiconductors PXN2020, Reference Manual, Page: 887 / 1376

Controller Area Network (FlexCAN)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 29-3
• Individual Rx mask registers per message buffer
• Includes 1056 bytes of RAM used for message buffer storage
• Includes 256 bytes of RAM used for individual Rx mask registers
• Full featured Rx FIFO with storage capacity for six frames and internal pointer handling
• Powerful Rx FIFO ID filtering, capable of matching incoming IDs against either eight extended,
16 standard, or 32 partial (8 bits) IDs, with individual masking capability
• Selectable backwards compatibility with previous FlexCAN version
• Programmable clock source to the CAN protocol interface, either bus clock or crystal oscillator
• Unused message buffer and Rx mask register space can be used as general-purpose RAM space
• Listen-only mode capability
• Programmable loop-back mode supporting self-test operation
• Programmable transmission priority scheme: lowest ID, lowest buffer number or local priority on
individual Tx message buffers.
• Hardware cancellation on Tx message buffers.
• Time stamp based on 16-bit free-running timer
• Global network time, synchronized by a specific message
• Maskable interrupts
• Independent of the transmission medium (an external transceiver is assumed)
• Short latency time due to an arbitration scheme for high-priority messages
• Low-power modes
29.1.3 Modes of Operation
There are four main operating modes of FlexCAN: normal, freeze, listen-only, and loop-back. One
low-power mode is supported: module disable. For more details, refer to
Section 29.4.8, Modes of
Operation Details.
29.1.3.1 Normal Mode
In normal mode the module operates receiving and/or transmitting message frames, errors are handled
normally and all the CAN protocol functions are enabled. In the MCU, there is no distinction between user
and supervisor modes.
29.1.3.2 Freeze Mode
Freeze mode is entered when the FRZ bit in the module configuration register (CAN x _MCR) is asserted,
while the HALT bit in CAN x _MCR is set, or if debug mode is requested by either core. In freeze mode no
transmission or reception of frames is done, and synchronicity to the CAN bus is lost.