NXP Semiconductors PXN2020, Reference Manual, Page: 882 / 1376

Enhanced Modular Input/Output Subsystem (eMIOS200)
PXN20 Microcontroller Reference Manual, Rev. 1
28-60 Freescale Semiconductor
28.8 Initialization/Application Information
On resetting the eMIOS200 all unified channels enter GPIO input mode.
28.8.1 Considerations
Before changing an operating mode, the unified channel must be programmed to GPIO mode and
EMIOS_CADR[
n ] and EMIOS_CBDR[ n ] registers must be updated with the correct values for the next
operating mode. Then the EMIOS_CCR[ n ] register can be written with the new operating mode. If a
unified channel is changed from one mode to another without performing this procedure, the first operation
cycle of the selected time base can be random, i.e., matches can occur in random time if the contents of
EMIOS_CADR[
n ] or EMIOS_CBDR[ n ] were not updated with the correct value before the time base
matches the previous contents of EMIOS_CADR[ n ] or EMIOS_CBDR[ n ].
When interrupts are enabled, the software must clear the FLAG bits before exiting the interrupt service
routine.
28.8.2 Application Information
Correlated output signals can be generated by all output operation modes. The OU[ n ] bits in
EMIOS_OUDR can be used to control the update of these output signals.
In order to guarantee the internal counters of correlated channels are incremented in the same clock cycle,
the internal prescalers must be set before enabling the global prescaler. If the internal prescalers are set
after enabling the global prescaler, the internal counters may increment in the same ratio but at a different
clock cycle.
It is recommended to drive output disable input signals with the emios_flag_out signals of some unified
channels running in SAIC mode. When an output disable condition happens, the software interrupt routine
must service the output channels before servicing the channels running SAIC. This procedure avoids
glitches in the output pins.
28.8.3 Time Base Generation
For MC, OPWFM, and OPWM with internal clock source operation modes, the internal counter rate can
be modified by configuring the clock prescaler ratio.
Figure 28-57 shows an example of a time base with
prescaler ratio equal to one. When the prescaler is greater than one, the counter is immediately cleared on
a match and then incremented in the next prescaled clock edge, except when running in OPWFM mode or
MC mode with internal clock source. In these cases, the counter will skip the next prescaled clock edge
and continue incremented on subsequent edges, as shown in
Figure 28-58 .
NOTE
MCB, OPWFMB, and OPWMB modes have a different behavior.