NXP Semiconductors PXN2020, Reference Manual, Page: 789 / 1376

Media Local Bus (MLB)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 27-17
27.3.2.11 Channel n Entry Configuration Register
The Channel n Entry Configuration Register (CECR n ) defines basic attributes about a given logical
channel, such as the channel enable, channel type, channel direction, and channel address. The definitions
of some of the bit fields in the CECR
n register vary depending on the selected channel type.
Offset: ML 0x0030 Access: User read-only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0
0
0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R CSU[15:0]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-11. Channel Interrupt Configuration Register (CICR)
Table 27-17. CICR Field Descriptions
Field Description
CSU
[15:0]
Channel Status Update for Logical Channels 15 through 0. When set, these bits indicate that hardware has
generated an interrupt for the appropriate channel. These bits are sticky and can only be cleared by a software write.
Writing to the CICR register has no effect. To clear a particular bit in the CICR, software must clear all of the
unmasked status bits in the corresponding CSCRn register.
0 Channel n has not generated an interrupt.
1 Channel n has generated an interrupt.
Offset: 0x0040 (CECR0)
0x0050 (CECR1)
0x0060 (CECR2)
0x0070 (CECR3)
0x0080 (CECR4)
0x0090 (CECR5)
0x00A0 (CECR6)
0x00B0 (CECR7) 0x00C0 (CECR8)
0x00D0 (CECR9)
0x00E0 (CECR10)
0x00F0 (CECR11) 0x0100 (CECR12)
0x0110 (CECR13)
0x0120 (CECR14)
0x0130 (CECR15) Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
CE TR CT[1:0]
FSE/
FCE
MDS[1:0]
0 0
MLFS
0
MBE MBS MBD MDB MPE
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R FSCD
IPL[7]
IPL[6:5] FSPC[4:0] / IPL[4:0] CA[8:1]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 27-12. Channel n Entry Configuration Register (CECRn)