NXP Semiconductors PXN2020, Reference Manual, Page: 629 / 1376

FlexRay Communication Controller (FlexRAY)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 26-15
26.5.2.5 System Memory Base Address Register (SYMBADR)
CLKSEL Protocol Engine Clock Source Select — This bit is used to select the clock source for the protocol engine.
0 PE clock source is generated by on-chip crystal oscillator.
1 PE clock source is generated by on-chip PLL.
BITRATE FlexRay Bus Bit Rate — This bit field defines the FlexRay Bus Bit Rate.00010.0 Mbit/sec
000 10.0 Mbit/sec
001 5.0 Mbit/sec
010 2.5 Mbit/sec
011 8.0 Mbit/sec
100 reserved
101 reserved
110 reserved
111 reserved
Table 26-9. FlexRay Channel Selection
SCM CHB CHA Description
Dual Channel Device Modes
0
0 0
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN not driven by controller
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by controller
0 1
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN driven by controller - connected to FlexRay channel A
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by controller
1 0
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN not driven by controller
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN driven by controller - connected to FlexRay channel B
1 1
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN driven by controller - connected to FlexRay channel A
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN driven by controller - connected to FlexRay channel B
Single Channel Device Mode
1
0 0
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN not driven by controller
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by controller
0 1
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN driven by controller - connected to FlexRay channel A
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by controller
1 0
ports FR_A_RX, FR_A_TX, and FR_A_TX_EN driven by controller - connected to FlexRay channel B
ports FR_B_RX, FR_B_TX, and FR_A_TX_EN not driven by controller
1 1 reserved
Base + 0x0004 Write: Disabled Mode
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R
SMBA[31:16]
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 26-4. System Memory Base Address High Register (SYMBADHR)
Table 26-8. MCR Field Descriptions
Field Description