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Fast Ethernet Controller (FEC)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
25-47
NOTE
Whenever the software driver sets an E bit in one or more receive
descriptors, the driver should follow that with a write to RDAR.
25.5.3
Ethernet Transmit Buffer Descriptor (TxBD)
Data is presented to the FEC for transmission by arranging it in buffers referenced by the channel’s TxBDs.
The Ethernet controller confirms transmission by clearing the ready bit (R bit) when DMA of the buffer is
complete. In the TxBD the user initializes the R, W, L, and TC bits and the length (in bytes) in the first
word, and the buffer pointer in the second word.
The FEC sets the R bit = 0 in the first word of the BD when the buffer has been DMA’d. Status bits for the
buffer/frame are not included in the transmit buffer descriptors. Transmit frame status is indicated via
individual interrupt bits (error conditions) and in statistic counters in the MIB block. See
MIB Block Counters Memory Map,
for more details.
.
2
Bits [0:15]
Data Length Data length. Written by the FEC. Data length is the number of 8-bit data groups
(octets) written by the FEC into this BD’s data buffer if L = 0 (the value is equal to
EMRBR), or the length of the frame including CRC if L = 1. It is written by the FEC
once as the BD is closed.
4
Bits [0:15]
A[0:15]]
RX data buffer pointer, bits [0:15]
1
6
Bits [0:15]
A[16:31]
RX data buffer pointer, bits [16:31]
1
The receive buffer pointer, which contains the address of the associated data buffer, must always be evenly divisible by 16.
The buffer must reside in memory external to the FEC. This value is never modified by the Ethernet controller.
0 1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
0
R
TO1
W
TO2
L
TC
ABC
—
—
—
—
—
—
—
—
—
2
Data Length
4
Tx Data Buffer Pointer - A [0:15]
6
Tx Data Buffer Pointer - A [16:31]
Figure 25-29. Transmit Buffer Descriptor (TxBD)
Table 25-36. Receive Buffer Descriptor Field Definitions (continued)
Halfword
Location
Field Name
Description
Summary of Contents for PXN2020
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