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Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
1-15
1.7.16
Enhanced Direct Memory Access Controller (eDMA)
The following summarizes the PXN20 implementation of the eDMA controller:
•
Support independent 8, 16 or 32 bit single value or block transfers
•
Supports variable sized queues and circular queues
•
Source and destination address registers are independently configured to post-increment or remain
constant
•
Each transfer is initiated by a peripheral, CPU, periodic timer interrupt or eDMA channel request
•
Each eDMA channel can optionally send an interrupt request to the CPU on completion of a single
value or block transfer
•
DMA transfers possible between system memories, SPIs, I
2
C, ADC, UART, eMIOS200 and
General Purpose I/Os
•
Programmable DMA channel mux allows assignment of any DMA source to any available DMA
channel with up to a total of 64 potential request sources.
1.7.17
Crossbar Switch (XBAR)
The Crossbar Switch allows concurrent accesses between masters and slaves, and provides these features:
•
Up to 6 master ports
— Masters: Z6 CPU, Z0 CPU, eDMA, FlexRay, FEC, MLB
•
Multiple bus slaves to enable access to flash, SRAM ports and peripherals
•
Multiple AIPS bridges to support connection to all peripheral modules
•
Crossbar supports consecutive transfers from master to available slaves
•
32-bit internal address bus, 32-bit internal data bus
•
User configurable priority arbitration based for masters
•
Temporary dynamic priority elevation for IOP and DMA
1.7.18
Memory Protection Unit (MPU)
The MPU provides the following features:
•
Supports up to 16 region descriptors for per-master protection
•
Start and end address defined with 32-byte granularity
•
Overlapping regions supported
•
Protection attributes can optionally include process ID
•
Protection offered for 4 concurrent read ports
•
Read and write attributes for all masters
•
Execute and supervisor/user mode attributes for processor masters
NOTE
The MPU is available on the PXN20 only.
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
Page 372: ...e200z6 Core Z6 PXN20 Microcontroller Reference Manual Rev 1 13 8 Freescale Semiconductor...
Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...