NXP Semiconductors PXN2020, Reference Manual, Page: 554 / 1376

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
24-34 Freescale Semiconductor
Figure 24-21. eDMA Operation, Part 3
24.5 Initialization / Application Information
24.5.1 eDMA Initialization
A typical initialization of the eDMA has the following sequence:
1. Write the EDMA_CR if a configuration other than the default is desired.
2. Write the channel priority levels into the EDMA_CPR n registers if a configuration other than the
default is desired.
3. Enable error interrupts in the EDMA_EEIRL and/or EDMA_EEIRH registers if desired.
4. Write the 32-byte TCD for each channel that may request service.
5. Enable any hardware service requests via the EDMA_ERQRH and/or EDMA_ERQRL registers.
6. Request channel service by software (setting the TCD.START bit) or by hardware (slave device
asserting its DMA peripheral request signal).
After any channel requests service, a channel is selected for execution based on the arbitration and priority
levels written into the programmer's model. The DMA engine reads the entire TCD, including the primary
Slave in
terface
eDMA
eDMA done
System bus
Slave write data
Slave write address
Bus write data
Slave read data
Bus address
eDMA engine
TCD0
TCD n -1*
eDMA peripheral
Bus read data
request
SRAM
Transfer control descriptor
(TCD)
SRAM
Data path
Address
path
Control
Program model/
channel arbitration
*n = 32 channels