NXP Semiconductors PXN2020, Reference Manual, Page: 55 / 1376

Introduction
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 1-13
• Programmable clock source
— System clock
— Direct oscillator clock to avoid PLL jitter
— Listen only mode capabilities
1.7.11 Inter-IC Communications Module (I
2
C)
The I
2
C module features the following:
• Two-wire bi-directional serial bus for on-board communications
• Compatibility with I
2
C bus standard
• Multimaster operation
• Software-programmable for one of 256 different serial clock frequencies
• Software-selectable acknowledge bit
• Interrupt-driven, byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• Start and stop signal generation/detection
• Repeated START signal generation
• Acknowledge bit generation/detection
• Bus-busy detection
1.7.12 Serial Peripheral Interface Module (SPI)
The PXN20 SPI features the following:
• Full duplex, synchronous transfers
• Master or slave operation
• Programmable master bit rates
• Programmable clock polarity and phase
• End-of-transmission interrupt flag
• Programmable transfer baud rate
• Programmable data frames from 4 to 16 bits
• Up to 24 chip select lines available (6 per SPI module); the number available at any time is
dependent on package and pin multiplexing.
• Up to 4 independently configurable transfer types can be configured for each SPI using the clock
and transfer attributes registers
• Chip select strobe available as alternate function on one of the chip select pins for de-glitching
• FIFOs for buffering up to 4 transfers on the transmit and receive side
• General purpose I/O functionality on pins when not used for SPI
• Queueing operation possible through use of eDMA