NXP Semiconductors PXN2020, Reference Manual, Page: 539 / 1376

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-19
24.3.2.12 eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
The EDMA_CDSBR provides a memory-mapped mechanism to clear the DONE bit in the TCD of the
given channel. The data value on a register write causes the DONE bit in the corresponding transfer control
descriptor to be cleared. Setting bit 1 (CDSB[0]) provides a global clear function, forcing all DONE bits
to be cleared.
If bit 0 is set, the CDSB command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
24.3.2.13 eDMA Interrupt Request Register (EDMA_IRQRL)
The EDMA_IRQRL provides a bit map for the 32 channels signaling the presence of an interrupt request
for each channel. EDMA_IRQRL maps to channels 31–0.
Table 24-13. EDMA_SSBR Field Descriptions
Field Description
NOP No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
SSB[0:6] Set START Bit (channel service request).
0–31
Set the corresponding channel’s TCD START bit.
32–63 Reserved.
64–127 Set all TCD START bits.
Note: Bits 2 and 3 (SSBR[1:2]) are not used.
Offset: EDM 0x001F Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP CDSB[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 24-13. eDMA Clear DONE Status Bit Register (EDMA_CDSBR)
Table 24-14. EDMA_CDSBR Field Descriptions
Field Description
NOP No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
CDSB[0:6] Clear DONE Status Bit.
0–31
Clear the corresponding channel’s DONE bit.
32–63 Reserved.
64–127 Clear all TCD DONE bits.
Note: Bits 2 and 3 (CDSBR[1:2]) are not used.