NXP Semiconductors PXN2020, Reference Manual, Page: 537 / 1376

Enhanced Direct Memory Access Controller (eDMA)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 24-17
24.3.2.9 eDMA Clear Interrupt Request Register (EDMA_CIRQR)
The EDMA_CIRQR provides a memory-mapped mechanism to clear a given bit in the EDMA_IRQRL to
disable the interrupt request for a given channel. The given value on a register write causes the
corresponding bit in the EDMA_IRQRL to be cleared. Setting bit 1 (CINT[0]) provides a global clear
function, forcing the entire contents of the EDMA_IRQRL to be zeroed, disabling all eDMA interrupt
requests. Reads of this register return all zeroes.
If bit 0 is set, the CINT command is ignored. This allows multiple byte registers to be written as a 32-bit
word. Reads of this register return all zeroes.
Table 24-10. EDMA_CEEIR Field Descriptions
Field Description
NOP No operation.
0 Normal operation.
1 No operation, ignore bits 1–7.
CEEI[0:6] Clear Enable Error Interrupt.
0–31
Clear corresponding bit in EDMA_EEIRL.
32–63 Reserved.
64–127 Clear all bits in EDMA_EEIRL.
Note: Bits 2 and 3 (CEEIR[1:2]) are not used.
Offset: EDM 0X001C Access: User write-only
0 1 2 3 4 5 6 7
R
W NOP CINT[0:6]
Reset 0 0 0 0 0 0 0 0
Figure 24-10. eDMA Clear Interrupt Request (EDMA_CIRQR)
Table 24-11. EDMA_CIRQR Field Descriptions
Field Description
NOP No operation.
0 Normal operation.
1 No operation, ignore bits 1-7.
CINT[0:6]
Clear Interrupt Request.
0–31
Clear corresponding bit in EDMA_IRQRL.
32–63 Reserved.
64–127 Clear all bits in EDMA_IRQRL.
Note: Bits 2 and 3(CIRQR[1:2]) are not used.