NXP Semiconductors PXN2020, Reference Manual, Page: 503 / 1376

Periodic Interrupt Timer (PIT)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 22-9
Figure 22-9. Dynamically Setting a New Load Value
22.4.2 Debug Mode
In debug mode, the timers are frozen. This is intended to aid software development, allowing the developer
to halt the processor, investigate the current state of the system (e.g., the timer values), and then continue
the operation.
22.4.3 Interrupts
All of the timers support interrupt generation. See Chapter 10, Interrupts and Interrupt Controller (INTC),
for related vector addresses and priorities.
Timer interrupts can be disabled by setting the TIE bits to 0. The timer interrupt flags (TIF) are set to 1
when a timeout occurs on the associated timer, and are cleared to 0 by writing a 1 to that TIF bit.
22.5 Initialization and Application Information
22.5.1 Example Configuration
In the example configuration:
• The PIT clock has a frequency of 50 MHz
• Timer 1 creates an interrupt every 5.12 ms
• Timer 8 creates a trigger event every 30 ms.
First the PIT module needs to be activated by writing a 0 to the MDIS bit in the PITMCR register.
The 50 MHz clock frequency equates to a clock period of 20 ns and the 10 MHz frequency equates to a
clock period of 100 ns. Timer 1 needs to trigger every 5.12 ms/20 ns = 256,000 cycles, and Timer 8 needs
to trigger every 30 ms/20 ns = 1,500,000 cycles. The value for the LDVAL
n register trigger would be
calculated as (period / clock period) – 1.
This means that LDVAL1 will be written with 0x0003_E7FF, and LDVAL8 with 0x0016_E35F.
Enable the interrupt for Timer 1 is doing the following:
1. Clear TIF in TFLG1. (If TIF is set, an interrupt occurs immediately when Timer 1 is enabled.)
2. Set TIE in the TCTRL1 register.
3. Start the timer by writing a 1 to bit TEN in the TCTRL1 register.
p1 p1
Timer Enabled New Start
Value p2 set
p1 p2
Start Value = p1
p2
Trigger
Event