NXP Semiconductors PXN2020, Reference Manual, Page: 496 / 1376

Periodic Interrupt Timer (PIT)
PXN20 Microcontroller Reference Manual, Rev. 1
22-2 Freescale Semiconductor
22.1.2 Features
The PIT has these major features:
• Eight 32-bit timers generating DMA trigger pulses
• All timers can be configured to generate interrupts instead of triggers
• Timer 3 can be the source of an ADC trigger input via SIU configuration
• Timers share one common core clock
• Independent timeout periods for each timer
22.1.3 Modes of Operation
There are two main operating modes of PIT: run mode and halt mode. In run mode, bit 7 = 0 in the
SIU_HLT0 register and all functional parts of the PIT module are running. In halt mode, bit 7 = 1 in the
SIU_HLT0 register, and the clock to the PIT module is disabled, halting the module.
22.2 Signal Description
22.2.1 External Signal Description
The PIT module has no external signals.
22.3 Memory Map and Registers
This section provides a detailed description of all PIT registers.
22.3.1 Module Memory Map
The PIT memory map is shown in Table 22-2 . The address of each register is given as an offset to the PIT
base address. Registers are listed in address order, identified by complete name and mnemonic, with the
type of accesses allowed.
Table 22-1. Timer Features
Timer
Interrupt
Vector Number
DMA Trigger ADC Trigger CTU Trigger
1 149 X
2 150 X
3 151 X X
4 152 X X
5 153 X
6 154 X
7 155 X
8 156 X