NXP Semiconductors PXN2020, Reference Manual, Page: 482 / 1376

Software Watchdog Timer (SWT)
PXN20 Microcontroller Reference Manual, Rev. 1
20-4 Freescale Semiconductor
20.3.2.2 SWT Interrupt Register (SWT_IR)
The SWT_IR contains the time-out interrupt flag.
20.3.2.3 SWT Time-Out Register (SWT_TO)
The SWT Time-Out (SWT_TO) register contains the 32-bit time-out period. This register is read-only if
either the SWT_CR[HLK] or SWT_CR[SLK] bits are set.
SLK Soft Lock. This bit is cleared by writing the unlock sequence to the service register.
0 SWT_CR, SWT_TO SWT_WN and SWT_SK are read/write registers if HLK = 0.
1 SWT_CR, SWT_TO, SWT_WN and SWT_SK are read-only registers.
FRZ Debug Mode Control. Allows the watchdog timer to be stopped when the device enters debug mode.
0 SWT counter continues to run in debug mode.
1 SWT counter is stopped in debug mode.
WEN Watchdog Enabled.
0 SWT is disabled.
1 SWT is enabled.
Offset: SW 0x0004 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
R 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R 0 0 0 0 0 0 0 0 0
0
0 0 0 0 0 TIF
W w1c
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
Figure 20-2. SWT Interrupt Register (SWT_IR)
Table 20-3. SWT_IR Field Descriptions
Field Description
TIF Time-out Interrupt Flag. The flag and interrupt are cleared by writing a 1 to this bit. Writing a 0 has no effect.
0 No interrupt request.
1 Interrupt request due to an initial time-out.
Table 20-2. SWT_CR Field Descriptions
Field Description