NXP Semiconductors PXN2020, Reference Manual, Page: 479 / 1376

PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 20-1
Chapter 20
Software Watchdog Timer (SWT)
20.1 Introduction
The Software Watchdog Timer (SWT) is a peripheral module that can prevent system lockup in situations
such as software getting trapped in a loop or if a bus transaction fails to terminate. When enabled, the SWT
requires periodic execution of a watchdog servicing operation. The servicing operation resets the timer to
a specified time-out period. If this servicing action does not occur before the timer expires, the SWT
generates an interrupt or hardware reset. The SWT can be configured to generate a reset or interrupt on an
initial time-out. A reset is always generated on a second consecutive time-out.
The SWT is clocked only from the 16 MHz IRC clock. This clock source is independent from the other
system clocks and hence offers an improved level of safety, since supporting only a single clock source
eliminates any risk of incorrect clock selection.
The SWT is reset in Sleep mode. The user can select whether the SWT runs in other modes with the
SIU_HLT1 register.
20.1.1 Features
The SWT has the following features:
• 32-bit time-out register to set the time-out period
• Programmable selection of window mode or regular servicing
• Programmable selection of reset or interrupt on an initial time-out
• Programmable selection of fixed or keyed servicing
• Master access protection
• Hard and soft configuration lock bits
20.1.2 Modes of Operation
The SWT supports two device modes of operation: normal and debug. When the SWT is enabled in normal
mode, its counter runs continuously. In debug mode, operation of the counter is controlled by the FRZ bit
in the SWT_CR. If the FRZ bit is set, the counter is stopped in debug mode, otherwise it continues to run.
20.2 External Signal Description
The SWT module does not have any external interface signals.