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AMBA Crossbar Switch (AXBS)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
16-9
16.3.2
General Operation
When a master makes an access to the AXBS from an idle master state, the access is taken immediately
by the AXBS. If the targeted slave port of the access is available (that is, the requesting master is currently
granted ownership of the slave port), the access is immediately presented on the slave port. It is possible
to make single clock (zero wait state) accesses through the AXBS by a granted master. If the targeted slave
port of the access is busy or parked on a different master port, the requesting master receives wait states
until the targeted slave port can service the master request. The latency in servicing the request depends
on each master’s priority level and the responding slave’s access time.
Because the AXBS appears to be simply another slave to the master device, the master device has no
indication that it owns the slave port it is targeting. While the master does not have control of the slave port
it is targeting, it is wait-stated.
A master is given control of a targeted slave port only after a previous access to a different slave port has
completed, regardless of its priority on the newly targeted slave port. This prevents deadlock from
occurring when a master has the following conditions:
•
Outstanding request to slave port A that has a long response time
•
Pending access to a different slave port B
•
Lower priority master also makes a request to the different slave port B.
In this case, the lower priority master is granted bus ownership of slave port B after a cycle of arbitration,
assuming the higher priority master slave port A access is not terminated.
After a master has control of the slave port it is targeting, the master remains in control of that slave port
until it gives up the slave port by running an IDLE cycle, leaves that slave port for its next access, or loses
control of the slave port to a higher priority master with a request to the same slave port. However, because
all masters run a fixed-length burst transfer to a slave port, it retains control of the slave port until that
transfer sequence is completed. In round-robin arbitration mode, the current master is forced to hand off
bus ownership to an alternately requesting master at the end of its current transfer sequence.
When a slave bus is idled by the AXBS, it can be parked on the master port using the PARK bits in the
XBAR_SGPCR (slave general-purpose control register), or on the last master to have control of the slave
port. This can avoid the initial clock of the arbitration delay if the master must arbitrate to gain control of
the slave port. The slave port can also be put into low-power park mode to save power.
16.3.3
Master Ports
The AXBS terminates an access and it is not allowed to pass through the AXBS unless the master currently
is granted access to the slave port to which the access is targeted. A master access is taken if the slave port
to which the access decodes is either currently servicing the master or is parked on the master. In this case,
the AXBS is completely transparent and the master access is immediately transmitted on the slave bus and
no arbitration delays are incurred. A master access stall if the access decodes to a slave port that is busy
serving another master, parked on another master or is in low-power park mode.
If the slave port is currently parked on another master or is in low-power park mode, and no other master
is requesting access to the slave port, then only one clock of arbitration is incurred. If the slave port is
currently serving another master of a lower priority and the master has a higher priority than all other
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
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Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
Page 822: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 27 50 Freescale Semiconductor...
Page 1376: ...Memory Map PXN20 Microcontroller Reference Manual Rev 1 A 118 Freescale Semiconductor...