Flash Memory Array and Control
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor
12-13
12.3.2.4
Secondary Low/Mid Address Space Block Locking Register (SLL)
The Secondary Low/Mid Address Block Locking Register (SLL) provides an alternative means to protect
blocks from being modified. This has the effect of creating a “tiered” locking scheme to enable different
flash users to provide different default locking on blocks. These bits, along with bits in the LLOCK (LML),
determine if the block is locked from program or erase. An “OR” of LML and SLL determine the final
lock status.
NOTE
A reset value of 1* in
indicates that the reset value of these
registers is determined by Flash values in the shadow block. An erased
shadow block causes the reset value to be 1.
The SLL register is shown in
.
Offset: FLASH_REG 0x0008
Access: User read/write
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
R HBE
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
W
Reset
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
R
0
0
0
0
0
0
0
0
0
0
HLOCK
W
Reset
0
0
0
0
0
0
0
0
0
0
1*
1*
1*
1*
1*
1*
Figure 12-5. High Address Space Block Locking Register (HBL)
Table 12-6. HBL Field Descriptions
Field
Description
HBE
High Address Lock Enable This bit is used to enable the Lock registers (HLOCK) to be set or cleared by
register writes. This bit is a status bit only, and may not be written or cleared, and the reset value is 0. The
method to set this bit is to provide a password, and if the password matches, the HBE bit is set to reflect the
status of enabled, and is enabled until a reset operation occurs. For HBE, the password 0xB2B2_2222 must
be written to the HBL register.
0 High Address Locks are disabled, and cannot be modified.
1 High Address Locks are enabled to be written.
HLOCK[5:0]
High Address Space Block Lock. HLOCK has the same characteristics as LLOCK. Please see this description
for more information. The block numbering for High Address Space starts with HLOCK[0] and continues until
all blocks are accounted.
HLOCK is not writable unless HBE is high.
Summary of Contents for PXN2020
Page 1: ...PXN20 Microcontroller Reference Manual Devices Supported PXN2020 PXN2120 PXN20RM Rev 1 06 2011...
Page 42: ...PXN20 Microcontroller Reference Manual Rev 1 lxiv Freescale Semiconductor...
Page 64: ...Introduction PXN20 Microcontroller Reference Manual Rev 1 1 22 Freescale Semiconductor...
Page 112: ...Signal Description PXN20 Microcontroller Reference Manual Rev 1 3 44 Freescale Semiconductor...
Page 118: ...Resets PXN20 Microcontroller Reference Manual Rev 1 4 6 Freescale Semiconductor...
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Page 412: ...e200z0 Core Z0 PXN20 Microcontroller Reference Manual Rev 1 14 14 Freescale Semiconductor...
Page 821: ...Media Local Bus MLB PXN20 Microcontroller Reference Manual Rev 1 Freescale Semiconductor 27 49...
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