NXP Semiconductors PXN2020, Reference Manual, Page: 223 / 1376

System Integration Unit (SIU)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 8-41
8.3.2.24 Halt Acknowledge Register (SIU_HLTACKn)
The SIU_HLTACK n bits indicate that the peripheral requested to halt via the HLT n bit has completed its
halt process and has entered a halted state with the peripheral clocks disabled. The HLTACK n bits are
read-only; writes have no effect.
Offset: SI 0x09A8 Access: User read-only
0
1
1
1
2
2
3 4 5
2
6
2
7
2
8
2
9
2
10
2
11
2
12
2
13
2
14
2
15
2
R 0 0 0
HLT
3
HLT
4
0 0 0 0 0 0 0 0 0 0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
16
2
17
2
18
2
19
2
20 21 22 23 24
2
25
2
26 27 28 29 30
2
31
2
R 0 0 0 0
HLT
20
HLT
21
HLT
22
HLT
23
0 0
HLT
26
HLT
27
HLT
28
HLT
29
0 0
W
Reset 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Reserved, do not write to this bit.
2
Writes to this bit are reflected in the SIU_HLT1 and SIU_HLTACK1 register, but have no other effect.
Figure 8-27. Halt Register 1 (SIU_HLT1)
Table 8-28. SIU_HLT1 Register Field Descriptions
Field Description
HLT3 Halt bit 3. Setting this bit halts the DMA module.
HLT4 Halt bit 4. Setting this bit halts the NPC module.
HLT20 Halt bit 20. Setting this bit halts the ESCI_M module.
HLT21 Halt bit 21. Setting this bit halts the ESCI_L module.
HLT22 Halt bit 22. Setting this bit halts the ESCI_K module.
HLT23 Halt bit 23. Setting this bit halts the ESCI_J module.
HLT26 Halt bit 26. Setting this bit halts the DSPI_D module.
HLT27 Halt bit 27. Setting this bit halts the DSPI_C module.
HLT28 Halt bit 28. Setting this bit halts the I
2
C_D module.
HLT29 Halt bit 29. Setting this bit halts the I
2
C_C module.