NXP Semiconductors PXN2020, Reference Manual, Page: 145 / 1376

Clocks, Reset, and Power (CRP)
PXN20 Microcontroller Reference Manual, Rev. 1
Freescale Semiconductor 6-13
• Recovery vector for the Z0 core
• Reset for the Z0 core
NOTE
The user may attempt to set the CRP_Z6VEC[Z6RST] and
CRP_Z0VEC[Z0RST] bits to 1, but if one of these bits is already set to a
value of 1, the write to the other bit is blocked.
6.2.2.10 Reset Recovery Pointer Register (CRP_RECPTR)
The CRP_RECPTR register contains:
• Recovery pointer
• Fast recovery enable
Offset: CR 0x0054 Access: User read/write
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
Z0VEC Z0RST
0
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0
Figure 6-11. Z0 Reset Vector Register (CRP_Z0VEC)
Table 6-11. CRP_Z0VEC Field Descriptions
Field Description
Z0VEC Z0 Recovery Vector. The Z0VEC value determines the initial program counter for the Z0 when exiting reset.
On reset, the value contained in the register defaults to 0xFFFF_FFFE, and the Z0 is held in reset. Change
this value to point to a different memory location for Z0 specific initialization when negating the Z0RST bit or
recovering from Sleep mode.
Z0RST Controls the assertion of RESET to the Z0 core. Writes to this bit cause the Z0 to immediately enter/exit reset.
Reads of this bit indicate if the core is being held in reset.
0 Z0 not in reset.
1 Z0 in reset.
Offset: CR 0x0058 Access: User read only
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
R
RECPTR
FAST
REC
0
W
Reset 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0
Figure 6-12. Reset Recovery Pointer (CRP_RECPTR)