NXP Semiconductors PXN2020, Reference Manual, Page: 130 / 1376

System Clock Description
PXN20 Microcontroller Reference Manual, Rev. 1
5-12 Freescale Semiconductor
The Z6 and Z0 cores may be idled by their WAIT instructions. The WAIT instructions are used as a
power-saving feature to halt the core. Executing the WAIT instruction puts the corresponding core in an
idle state at a clean transition point. When the core stops, clocks to the core are gated off, and the core
asserts a signal indicating it is waiting for an interrupt. The state of this signal is software accessible via
the appropriate SIU_HLTACK0 and SIU_HLTACK1 bits.
An interrupt to the corresponding core exits the WAIT instruction and the core continues to the appropriate
interrupt service routine (ISR).
NOTE
If both the Z6 and Z0 cores are stopped (either in WAIT or disabled with
ZxRST), then only an NMI interrupt will recover the core from WAIT. A
core may be recovered from WAIT with either an NMI or external interrupt
if the other core is not stopped.
5.5 Alternate Module Clock Domains
5.5.1 FlexCAN Clock Domains
The FlexCAN blocks have two distinct software-controlled clock domains. One of the clock domains is
always derived from the system clock. This clock domain includes the message buffer logic. The source
for the second clock domain can be the system clock or the 4 – 40 MHz XTAL output. The logic in the
second clock domain controls the CAN interface pins. The CLK_SRC bit in the FlexCAN CTRL register
selects between the system clock and the oscillator clock as the clock source for the second domain.
Selecting the oscillator as the clock source ensures low jitter on the CAN bus. System software can gate
both clocks by writing to the MDIS bit in the FlexCAN MCR register.
NOTE
To prevent improper FlexCAN behavior when switching of the system
clock or the CAN protocol engine clock source, or before the desired clock
source has stabilized, the FlexCAN module must first be disabled by setting
the CAN
x _MCR[MDIS] = 1.
If the oscillator clock source is selected, the frequency of the peripheral clock needs to be the same or
greater than the oscillator clock frequency.
If the 4 – 40 MHz XTAL is used as the system clock source and is divided down, then the clock source
selected for the CAN interface must be the system clock (i.e., the divided 4 – 40 MHz XTAL) to keep the
system clock not slower than the CAN interface clock.
5.5.2 FlexRay Clock Domains
The FlexRay block has two distinct software-controlled clock domains. One of the clock domains is
always derived from the system clock. The source for the second clock domain can be the system clock or
the 4 – 40 MHz XTAL output. The logic in the second clock domain controls the FlexRay interface pins.
The CLK_SRC bit in the FlexRay CTRL register selects between the system clock and the oscillator clock